On Wed, Oct 16, 2019 at 02:59:45PM +0000, Shankar, Uma wrote: > > > >-----Original Message----- > >From: Ville Syrjala <[email protected]> > >Sent: Wednesday, October 16, 2019 12:36 AM > >To: [email protected] > >Cc: Mun, Gwan-gyeong <[email protected]>; Shankar, Uma > ><[email protected]> > >Subject: [PATCH] drm/i915: Fix MST oops due to MSA changes > > > >From: Ville Syrjälä <[email protected]> > > > >The MSA MISC computation now depends on the connector state, and we do it > >from > >the DDI .pre_enable() hook. All that is fine for DP SST but with MST we > >don't actually > >pass the connector state to the dig port's .pre_enable() hook which leads to > >an oops. > > > >Need to think more how to solve this in a cleaner fashion, but for now let's > >just add a > >NULL check to stop the oopsing. > > Looks good to me. We will have to handle colorspaces for MST properly.
Yeah, in fact just realized that this is a transcoder register so we're no longer configuring MSA MISC for anything but the first MST stream. The other streams will leave TRANS_MSA_MISC untouched. So I guess we need to move this into the MST code proper, and if it needs to be left in ddi_pre_enable() for SST we probably want to exclude it getting programming there for MST there. Any volunteers? Pushed. Thanks for the reviews. > But that can be > done later. Thanks for identifying and fixing this. > Reviewed-by: Uma Shankar <[email protected]> > > >Cc: Gwan-gyeong Mun <[email protected]> > >Cc: Uma Shankar <[email protected]> > >Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP > >MSA") > >Signed-off-by: Ville Syrjälä <[email protected]> > >--- > > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > >b/drivers/gpu/drm/i915/display/intel_ddi.c > >index 80f8e2698be0..4c81449ec144 100644 > >--- a/drivers/gpu/drm/i915/display/intel_ddi.c > >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c > >@@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct > >intel_crtc_state > >*crtc_state, > > * of Color Encoding Format and Content Color Gamut] while sending > > * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields > > * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. > >+ * > >+ * FIXME MST doesn't pass in the conn_state > > */ > >- if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) > >+ if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state)) > > temp |= DP_MSA_MISC_COLOR_VSC_SDP; > > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); > >-- > >2.21.0 > -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
