Quoting Mika Kuoppala (2019-10-15 16:44:42) > In order to ensure constant caches are invalidated > properly with a0, we need extra hdc flush after invalidation. > > v2: use IS_TGL_REVID (Chris) > > References: HSDES#1604544889 > Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Chris Wilson <[email protected]> -Chris _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
- [Intel-gfx] [PATCH 01/11] drm/i915/tgl: Add IS_TGL_REVID Mika Kuoppala
- [Intel-gfx] [PATCH 04/11] drm/i915/tgl: Add extra hdc f... Mika Kuoppala
- Re: [Intel-gfx] [PATCH 04/11] drm/i915/tgl: Add ext... Chris Wilson
- [Intel-gfx] [PATCH 02/11] drm/i915/tgl: Include ro part... Mika Kuoppala
- [Intel-gfx] [PATCH 06/11] drm/i915/tgl: Wa_1409420604 Mika Kuoppala
- [Intel-gfx] [PATCH 11/11] drm/i915/tgl: Wa_1607138340 Mika Kuoppala
- [Intel-gfx] [PATCH 05/11] drm/i915/tgl: Keep FF dop clo... Mika Kuoppala
- [Intel-gfx] [PATCH 08/11] drm/i915/tgl: Wa_1409600907 Mika Kuoppala
- [Intel-gfx] [PATCH 03/11] drm/i915/tgl: Add HDC Pipelin... Mika Kuoppala
