On Wed, Sep 25, 2019 at 04:45:08PM -0700, José Roberto de Souza wrote: > Link training is failling when running link at 2.7GHz and 1.62GHz and > following BSpec pll algorithm. > > Comparing the values calculated and the ones from the reference table > it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set > to 5. For DP ports ICL mg pll algorithm sets it to 10 or 5 based on > div2 value, that matches with dkl hardcoded table. > > So implementing this way as it proved to work in HW and leaving a > comment so we know why it do not match BSpec. > > v4: > Using the same is_dp check as ICL, need testing on HDMI over tc port > > Issue reported on BSpec 49204. > > Signed-off-by: José Roberto de Souza <[email protected]>
Reviewed-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index 69abafa45ce9..be69a2344294 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -2630,13 +2630,13 @@ static bool icl_mg_pll_find_divisors(int clock_khz, > bool is_dp, bool use_ssc, > continue; > > if (div2 >= 2) { > - if (is_dkl) { > - a_divratio = 5; > - tlinedrv = 1; > - } else { > - a_divratio = is_dp ? 10 : 5; > - tlinedrv = 2; > - } > + /* > + * Note: a_divratio not matching TGL BSpec > + * algorithm but matching hardcoded values and > + * working on HW for DP alt-mode at least > + */ > + a_divratio = is_dp ? 10 : 5; > + tlinedrv = is_dkl ? 1 : 2; > } else { > a_divratio = 5; > tlinedrv = 0; > -- > 2.23.0 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
