DSB can access specific register, To identify those register which can be written through DSB, enum reg_write_cap is added to hold the capability.
Cc: Jani Nikula <[email protected]> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Animesh Manna <[email protected]> --- drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2abd199093c5..c4a17034d4dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -178,11 +178,22 @@ */ #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) +/* + * Added enum to hold the capability for those registers which can be written + * through DSB. + */ +enum reg_write_cap { + MMIO_WRITE, + DSB_WRITE, + DSB_INDEX_WRITE +}; + typedef struct { u32 reg; + enum reg_write_cap cap; } i915_reg_t; -#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) +#define _MMIO(r, ...) ((const i915_reg_t){ .reg = (r), ##__VA_ARGS__}) #define INVALID_MMIO_REG _MMIO(0) -- 2.22.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
