Chris Wilson <[email protected]> writes: > When inserting the final level PTE, we check that we are not overflowing > the page table (checking that pt_used does not exceed the size of the > table). However, we have to allow for every other PTE to be pinned by a > simultaneous removal thread (as on remove we bump the pt_used counter > before adjusting the table). > > Signed-off-by: Chris Wilson <[email protected]> > Cc: Mika Kuoppala <[email protected]>
Reviewed-by: Mika Kuoppala <[email protected]> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 081c8b79c047..94712d3eb882 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1112,7 +1112,8 @@ static int __gen8_ppgtt_alloc(struct i915_address_space > * const vm, > atomic_read(&pt->used)); > > atomic_add(count, &pt->used); > - GEM_BUG_ON(atomic_read(&pt->used) > I915_PDES); > + /* All other pdes may be simultaneously removed */ > + GEM_BUG_ON(atomic_read(&pt->used) > 2 * I915_PDES); > *start += count; > } > } while (idx++, --len); > -- > 2.23.0.rc1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
