On Thu, Jun 20, 2019 at 05:45:55PM -0700, José Roberto de Souza wrote: > EHL do not support 648 and 652.8 MHz. > > v2: > - Limiting maximum CD clock by max_cdclk_freq instead of remove it > from icl_calc_cdclk()(Ville and Jani) > > BSpec: 20598 > Cc: Clint Taylor <[email protected]> > Cc: Matt Roper <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Cc: Jani Nikula <[email protected]> > Signed-off-by: José Roberto de Souza <[email protected]>
Matches bspec. Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 8eef177b2bbd..daab4e9a6359 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2606,7 +2606,12 @@ static int intel_compute_max_dotclk(struct > drm_i915_private *dev_priv) > */ > void intel_update_max_cdclk(struct drm_i915_private *dev_priv) > { > - if (INTEL_GEN(dev_priv) >= 11) { > + if (IS_ELKHARTLAKE(dev_priv)) { > + if (dev_priv->cdclk.hw.ref == 24000) > + dev_priv->max_cdclk_freq = 552000; > + else > + dev_priv->max_cdclk_freq = 556800; > + } else if (INTEL_GEN(dev_priv) >= 11) { > if (dev_priv->cdclk.hw.ref == 24000) > dev_priv->max_cdclk_freq = 648000; > else > -- > 2.22.0 > -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
