On Wed, 27 Mar 2013 00:44:57 +0100 Daniel Vetter <[email protected]> wrote:
> We want to compute this earlier. To avoid a big complicated patch, > this patch here just does the big search&replace and still calls the > old functions at the same places. > > Signed-off-by: Daniel Vetter <[email protected]> > --- > drivers/gpu/drm/i915/intel_ddi.c | 8 ++++---- > drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++-------- > drivers/gpu/drm/i915/intel_dp.c | 2 +- > drivers/gpu/drm/i915/intel_drv.h | 4 +++- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > 5 files changed, 26 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index baeb470..3d09df0 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -931,7 +931,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) > if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { > > temp = TRANS_MSA_SYNC_CLK; > - switch (intel_crtc->bpp) { > + switch (intel_crtc->config.pipe_bpp) { > case 18: > temp |= TRANS_MSA_6_BPC; > break; > @@ -947,7 +947,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) > default: > temp |= TRANS_MSA_8_BPC; > WARN(1, "%d bpp unsupported by DDI function\n", > - intel_crtc->bpp); > + intel_crtc->config.pipe_bpp); > } > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); > } > @@ -969,7 +969,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc > *crtc) > temp = TRANS_DDI_FUNC_ENABLE; > temp |= TRANS_DDI_SELECT_PORT(port); > > - switch (intel_crtc->bpp) { > + switch (intel_crtc->config.pipe_bpp) { > case 18: > temp |= TRANS_DDI_BPC_6; > break; > @@ -984,7 +984,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc > *crtc) > break; > default: > WARN(1, "%d bpp unsupported by transcoder DDI function\n", > - intel_crtc->bpp); > + intel_crtc->config.pipe_bpp); > } > > if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index bfed546..b495629 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4648,6 +4648,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > const intel_limit_t *limit; > int ret; > > + /* temporary hack */ > + intel_crtc->config.dither = > + adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC; > + > for_each_encoder_on_crtc(dev, crtc, encoder) { > switch (encoder->type) { > case INTEL_OUTPUT_LVDS: > @@ -4748,7 +4752,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > /* default to 8bpc */ > pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); > if (is_dp) { > - if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { > + if (intel_crtc->config.dither) { > pipeconf |= PIPECONF_6BPC | > PIPECONF_DITHER_EN | > PIPECONF_DITHER_TYPE_SP; > @@ -4756,7 +4760,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > } > > if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { > - if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { > + if (intel_crtc->config.dither) { > pipeconf |= PIPECONF_6BPC | > PIPECONF_ENABLE | > I965_PIPECONF_ACTIVE; > @@ -5145,7 +5149,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc, > val = I915_READ(PIPECONF(pipe)); > > val &= ~PIPECONF_BPC_MASK; > - switch (intel_crtc->bpp) { > + switch (intel_crtc->config.pipe_bpp) { > case 18: > val |= PIPECONF_6BPC; > break; > @@ -5482,13 +5486,14 @@ static void ironlake_set_m_n(struct drm_crtc *crtc) > > if (!lane) > lane = ironlake_get_lanes_required(target_clock, link_bw, > - intel_crtc->bpp); > + intel_crtc->config.pipe_bpp); > > intel_crtc->fdi_lanes = lane; > > if (intel_crtc->config.pixel_multiplier > 1) > link_bw *= intel_crtc->config.pixel_multiplier; > - intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, > &m_n); > + intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock, > + link_bw, &m_n); > > I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m); > I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); > @@ -5651,8 +5656,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc > *crtc, > intel_crtc_update_cursor(crtc, true); > > /* determine panel color depth */ > - dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, > + dither = intel_choose_pipe_bpp_dither(crtc, fb, > + &intel_crtc->config.pipe_bpp, > adjusted_mode); > + intel_crtc->config.dither = dither; > if (is_lvds && dev_priv->lvds_dither) > dither = true; > > @@ -5822,8 +5829,10 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, > intel_crtc_update_cursor(crtc, true); > > /* determine panel color depth */ > - dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, > + dither = intel_choose_pipe_bpp_dither(crtc, fb, > + &intel_crtc->config.pipe_bpp, > adjusted_mode); > + intel_crtc->config.dither = dither; > > DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); > drm_mode_debug_printmodeline(mode); > @@ -8268,7 +8277,7 @@ static void intel_crtc_init(struct drm_device *dev, int > pipe) > dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; > dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; > > - intel_crtc->bpp = 24; /* default for pre-Ironlake */ > + intel_crtc->config.pipe_bpp = 24; /* default for pre-Ironlake */ > > drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); > } > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index d7c1403..34006f7 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -811,7 +811,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct > drm_display_mode *mode, > * the number of bytes_per_pixel post-LUT, which we always > * set up for 8-bits of R/G/B, or 3 bytes total. > */ > - intel_link_compute_m_n(intel_crtc->bpp, lane_count, > + intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane_count, > target_clock, adjusted_mode->clock, &m_n); > > if (HAS_DDI(dev)) { > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 63160c6..0ca0d76 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -195,6 +195,9 @@ struct intel_crtc_config { > */ > bool limited_color_range; > > + bool dither; > + int pipe_bpp; > + > /* Used by SDVO (and if we ever fix it, HDMI). */ > unsigned pixel_multiplier; > }; > @@ -230,7 +233,6 @@ struct intel_crtc { > int16_t cursor_x, cursor_y; > int16_t cursor_width, cursor_height; > bool cursor_visible; > - unsigned int bpp; > > struct intel_crtc_config config; > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > b/drivers/gpu/drm/i915/intel_hdmi.c > index 5508687..0731ba6 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -609,7 +609,7 @@ static void intel_hdmi_mode_set(struct drm_encoder > *encoder, > if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) > hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; > > - if (intel_crtc->bpp > 24) > + if (intel_crtc->config.pipe_bpp > 24) > hdmi_val |= HDMI_COLOR_FORMAT_12bpc; > else > hdmi_val |= SDVO_COLOR_FORMAT_8bpc; Reviewed-by: Jesse Barnes <[email protected]> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
