Op 04-06-2019 om 22:09 schreef Ville Syrjala: > From: Ville Syrjälä <[email protected]> > > On non-ULT HSW the "special" WRPLL reference clock select > actually means non-SSC. Take that into account when reading > out the WRPLL state. > > Also the non-SSC reference may be either 24MHz or 135MHz, > which we can read out from FUSE_STRAP3. The BDW docs actually > say: "also indicates whether the CPU and PCH are in a single > package or separate packages", so it may be that this is not > actually required and we could just assume 135 MHz (just like > the code already did). But it doesn't really hurt to read this > out as the HSW docs aren't quite so clear. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_ddi.c | 15 ++++++++++++++- > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b7dd42bfffaa..533b1d8d23cb 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7513,6 +7513,9 @@ enum { > #define ILK_DESKTOP (1 << 23) > #define HSW_CPU_SSC_ENABLE (1 << 21) > > +#define FUSE_STRAP3 _MMIO(0x42020) > +#define HSW_REF_CLK_SELECT (1 << 1) > + > #define ILK_DSPCLK_GATE_D _MMIO(0x42020) > #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) > #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index fc9bcbd75c3a..49dab3e72019 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1231,6 +1231,19 @@ static int hsw_ddi_calc_wrpll_link(struct > drm_i915_private *dev_priv, > wrpll = I915_READ(reg); > switch (wrpll & WRPLL_REF_MASK) { > case WRPLL_REF_SPECIAL_HSW: > + /* > + * muxed-SSC for BDW. > + * non-SSC for non-ULT HSW. Check FUSE_STRAP3 > + * for the non-SSC reference frequency. > + */ > + if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { > + if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT) > + refclk = 24; > + else > + refclk = 135; > + break; > + } > + /* fall through */ > case WRPLL_REF_PCH_SSC: > /* > * We could calculate spread here, but our checking > @@ -1243,7 +1256,7 @@ static int hsw_ddi_calc_wrpll_link(struct > drm_i915_private *dev_priv, > refclk = 2700; > break; > default: > - WARN(1, "bad wrpll refclk\n"); > + MISSING_CASE(wrpll); > return 0; > } >
Other patches look sane. Reviewed-by: Maarten Lankhorst <[email protected]> _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
