This is series fixes the WARN_ON that we see due to pipe_config mismatch on mipi dsi for icl. Only DSI0 trancoder regs are read even in case of dual link mode as the values programmed for DSI0 and DSI1 transcoder registers are same.
Vandita Kulkarni (3): drm/i915: Fix pipe config timing mismatch warnings drm/i915: Fix pipe config mismatch for bpp, output format drm/i915: Fix pixel clock and crtc clock config mismatch drivers/gpu/drm/i915/icl_dsi.c | 88 +++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_display.c | 3 +- 2 files changed, 89 insertions(+), 2 deletions(-) -- 1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
