From: Paulo Zanoni <[email protected]> I couldn't find any evidence that this register exists on Gen2+. On Gen 2/3/4 documents this register is listed as reserved and read-only. On the newer Gens this register is not even documented.
Also all we do with this register is: - Write 0 to it on i9xx_crtc_mode_set - Save/restore its value on the UMS code - Read it on intel_display_capture_error_state This commit fixes "unclaimed register" messages when there's a GPU hang on Haswell. Signed-off-by: Paulo Zanoni <[email protected]> --- drivers/gpu/drm/i915/i915_drv.h | 2 -- drivers/gpu/drm/i915/i915_reg.h | 3 --- drivers/gpu/drm/i915/i915_ums.c | 4 ---- drivers/gpu/drm/i915/intel_display.c | 4 ---- 4 files changed, 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ca6b215..9bf15e5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -513,7 +513,6 @@ struct i915_suspend_saved_registers { u32 savePIPEASTAT; u32 saveDSPASTRIDE; u32 saveDSPASIZE; - u32 saveDSPAPOS; u32 saveDSPAADDR; u32 saveDSPASURF; u32 saveDSPATILEOFF; @@ -544,7 +543,6 @@ struct i915_suspend_saved_registers { u32 savePIPEBSTAT; u32 saveDSPBSTRIDE; u32 saveDSPBSIZE; - u32 saveDSPBPOS; u32 saveDSPBADDR; u32 saveDSPBSURF; u32 saveDSPBTILEOFF; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4cf3ece..26e4b86 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3051,7 +3051,6 @@ #define DISPPLANE_TILED (1<<10) #define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) #define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188) -#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */ #define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190) #define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */ #define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */ @@ -3061,7 +3060,6 @@ #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) -#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) @@ -3109,7 +3107,6 @@ #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) #define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184) #define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188) -#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C) #define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190) #define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C) #define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4) diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c index 985a097..0e21925 100644 --- a/drivers/gpu/drm/i915/i915_ums.c +++ b/drivers/gpu/drm/i915/i915_ums.c @@ -160,7 +160,6 @@ void i915_save_display_reg(struct drm_device *dev) dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR); dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE); dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE); - dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS); dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR); if (INTEL_INFO(dev)->gen >= 4) { dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF); @@ -217,7 +216,6 @@ void i915_save_display_reg(struct drm_device *dev) dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR); dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE); dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE); - dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS); dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR); if (INTEL_INFO(dev)->gen >= 4) { dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF); @@ -390,7 +388,6 @@ void i915_restore_display_reg(struct drm_device *dev) /* Restore plane info */ I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE); - I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS); I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC); I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR); I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE); @@ -459,7 +456,6 @@ void i915_restore_display_reg(struct drm_device *dev) /* Restore plane info */ I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE); - I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS); I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC); I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR); I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0451056..b319cd3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4781,7 +4781,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, I915_WRITE(DSPSIZE(plane), ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); - I915_WRITE(DSPPOS(plane), 0); I915_WRITE(PIPECONF(pipe), pipeconf); POSTING_READ(PIPECONF(pipe)); @@ -9314,7 +9313,6 @@ struct intel_display_error_state { u32 control; u32 stride; u32 size; - u32 pos; u32 addr; u32 surface; u32 tile_offset; @@ -9350,7 +9348,6 @@ intel_display_capture_error_state(struct drm_device *dev) error->plane[i].stride = I915_READ(DSPSTRIDE(i)); if (INTEL_INFO(dev)->gen <= 3) error->plane[i].size = I915_READ(DSPSIZE(i)); - error->plane[i].pos = I915_READ(DSPPOS(i)); if (!IS_HASWELL(dev)) error->plane[i].addr = I915_READ(DSPADDR(i)); if (INTEL_INFO(dev)->gen >= 4) { @@ -9396,7 +9393,6 @@ intel_display_print_error_state(struct seq_file *m, seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); if (INTEL_INFO(dev)->gen <= 3) seq_printf(m, " SIZE: %08x\n", error->plane[i].size); - seq_printf(m, " POS: %08x\n", error->plane[i].pos); if (!IS_HASWELL(dev)) seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); if (INTEL_INFO(dev)->gen >= 4) { -- 1.7.10.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
