On Fri, Mar 22, 2019 at 08:09:50PM +0200, Ville Syrjälä wrote: > On Fri, Mar 22, 2019 at 10:58:01AM -0700, Manasi Navare wrote: > > On Fri, Mar 22, 2019 at 03:16:03PM +0200, Ville Syrjälä wrote: > > > On Fri, Mar 22, 2019 at 11:34:25AM +0200, Jani Nikula wrote: > > > > On Thu, 21 Mar 2019, Manasi Navare <[email protected]> wrote: > > > > > In case of tiled displays where different tiles are displayed across > > > > > different ports, we need to synchronize the transcoders involved. > > > > > This patch implements the transcoder port sync feature for > > > > > synchronizing one master transcoder with one or more slave > > > > > transcoders. This is only enbaled in slave transcoder > > > > > and the master transcoder is unaware that it is operating > > > > > in this mode. > > > > > This has been tested with tiled display connected to ICL. > > > > > > > > > > Cc: Daniel Vetter <[email protected]> > > > > > Cc: Ville Syrjälä <[email protected]> > > > > > Cc: Maarten Lankhorst <[email protected]> > > > > > Cc: Matt Roper <[email protected]> > > > > > Cc: Jani Nikula <[email protected]> > > > > > Signed-off-by: Manasi Navare <[email protected]> > > > > > --- > > > > > drivers/gpu/drm/i915/intel_display.c | 59 > > > > > ++++++++++++++++++++++++++++ > > > > > 1 file changed, 59 insertions(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > > > > b/drivers/gpu/drm/i915/intel_display.c > > > > > index 9980a4ed8c9c..16b46a3cb3bd 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > > > @@ -4009,6 +4009,62 @@ static void icl_set_pipe_chicken(struct > > > > > intel_crtc *crtc) > > > > > I915_WRITE(PIPE_CHICKEN(pipe), tmp); > > > > > } > > > > > > > > > > +static void icl_set_transcoder_port_sync(struct intel_atomic_state > > > > > *old_intel_state, > > > > > + const struct intel_crtc_state > > > > > *crtc_state) > > > > > +{ > > > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > > > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > > + struct intel_crtc_state *genlock_crtc_state = NULL; > > > > > + enum transcoder genlock_transcoder; > > > > > + u32 trans_ddi_func_ctl2_val; > > > > > + u8 master_select; > > > > > + > > > > > + /* > > > > > + * Port Sync Mode cannot be enabled for DP MST > > > > > + */ > > > > > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) > > > > > + return; > > > > > + > > > > > + /* > > > > > + * Configure the master select and enable Transcoder Port Sync > > > > > for > > > > > + * Slave CRTCs transcoder. > > > > > + */ > > > > > + if (!crtc_state->genlock_crtc) > > > > > + return; > > > > > + > > > > > + genlock_crtc_state = > > > > > intel_atomic_get_new_crtc_state(old_intel_state, > > > > > + > > > > > crtc_state->genlock_crtc); > > > > > + if (WARN_ON(!genlock_crtc_state)) > > > > > + return; > > > > > + > > > > > + genlock_transcoder = genlock_crtc_state->cpu_transcoder; > > > > > + switch (genlock_transcoder) { > > > > > + case TRANSCODER_A: > > > > > + master_select = 1; > > > > > + break; > > > > > + case TRANSCODER_B: > > > > > + master_select = 2; > > > > > + break; > > > > > + case TRANSCODER_C: > > > > > + master_select = 3; > > > > > + break; > > > > > + case TRANSCODER_EDP: > > > > > + default: > > > > > + master_select = 0; > > > > > + break; > > > > > + } > > > > > + /* Set the master select bits for Tranascoder Port Sync */ > > > > > + trans_ddi_func_ctl2_val = > > > > > I915_READ(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder)); > > > > > + trans_ddi_func_ctl2_val |= > > > > > (PORT_SYNC_MODE_MASTER_SELECT(master_select) & > > > > > + PORT_SYNC_MODE_MASTER_SELECT_MASK) > > > > > << > > > > > + PORT_SYNC_MODE_MASTER_SELECT_SHIFT; > > > > > > > > This doesn't do what you think it does. ITYM, > > > > > > > > val = I915_READ(); > > > > val &= ~FOO_MASK; > > > > val |= FOO_BAR; > > > > > > Also we alreayd have a place where we write this registers. Is there > > > some magic requirement why these bits can't be set there along with > > > eveyrthing else? > > > > We only write the bits of TRANS_DDI_FUNC_CTL currently but these bits > > are written to TRANS_DDI_FUNC_CTL2 and need to be written before enabling > > the transcoder. > > Thats why I created this separate function here to set the bits in > > TRANS_DDI_FUNC_CTL2 > > In that case there is no point in doing a rmw.
But isnt it always a good idea to do rmw? I mean what if the master select was set to something else earlier? Also could you look at the patch 1 of this series that assigns the genlock crtc pointer? Manasi > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
