The value of this registers will be used to test if PSR2 is doing selective update and if the number of blocks match with the expected.
v2: - Using new macros - Changed the string output Cc: Rodrigo Vivi <[email protected]> Cc: Dhinakaran Pandiyan <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> --- drivers/gpu/drm/i915/i915_debugfs.c | 32 +++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5ebf0e647ac7..4e92078bc65d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2621,10 +2621,34 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "Performance counter: %u\n", val); } - if ((psr->debug & I915_PSR_DEBUG_IRQ) && !psr->psr2_enabled) { - seq_printf(m, "Last attempted entry at: %lld\n", - psr->last_entry_attempt); - seq_printf(m, "Last exit at: %lld\n", psr->last_exit); + if (!psr->psr2_enabled) { + if (psr->debug & I915_PSR_DEBUG_IRQ) { + seq_printf(m, "Last attempted entry at: %lld\n", + psr->last_entry_attempt); + seq_printf(m, "Last exit at: %lld\n", psr->last_exit); + } + } else { + u8 frame; + + seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); + + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { + u32 su_blocks; + + /* + * Avoid register reads as each register contains more + * than one frame value + */ + if ((frame % 3) == 0) + val = I915_READ(PSR2_SU_STATUS(frame)); + + su_blocks = val & PSR2_SU_STATUS_MASK(frame); + su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); + /* Only printing frames with SU blocks */ + if (!su_blocks) + continue; + seq_printf(m, "%d\t%d\n", frame, su_blocks); + } } unlock: -- 2.20.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
