Having transitioned to using PIPECONTROL to combine the flush with the breadcrumb write using their post-sync functions, assume that this will resolve the serialisation with the subsequent MI_USER_INTERRUPT. That is when inspecting the breadcrumb after an interrupt we can rely on the write being posted (i.e. the HWSP will be coherent).
Testing using gem_sync shows that the PIPECONTROL + CS stall does serialise the command streamer sufficient that the breadcrumb lands before the MI_USER_INTERRUPT. The same is not true for MI_FLUSH_DW. Signed-off-by: Chris Wilson <[email protected]> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index eb3701fdeab6..5a1e4a65516e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2117,7 +2117,6 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 6) { engine->irq_enable = gen6_irq_enable; engine->irq_disable = gen6_irq_disable; - engine->irq_seqno_barrier = gen6_seqno_barrier; } else if (INTEL_GEN(dev_priv) >= 5) { engine->irq_enable = gen5_irq_enable; engine->irq_disable = gen5_irq_disable; @@ -2236,6 +2235,8 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb; engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz; + + engine->irq_seqno_barrier = gen6_seqno_barrier; } else { engine->emit_flush = bsd_ring_flush; if (IS_GEN(dev_priv, 5)) @@ -2260,6 +2261,7 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb; engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz; + engine->irq_seqno_barrier = gen6_seqno_barrier; return intel_init_ring_buffer(engine); } @@ -2279,6 +2281,7 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb; engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz; + engine->irq_seqno_barrier = gen6_seqno_barrier; return intel_init_ring_buffer(engine); } -- 2.20.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
