On Tue, Dec 11, 2018 at 09:30:43AM -0800, Bob Paauwe wrote: > It's not just GEN9 platforms that allow for pipes to be disabled via > the DFSM register, but all later platforms as well. > > Signed-off-by: Bob Paauwe <[email protected]> > --- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > b/drivers/gpu/drm/i915/intel_device_info.c > index 1e56319334f3..7ac641e8c0bd 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -811,7 +811,7 @@ void intel_device_info_runtime_init(struct > intel_device_info *info) > DRM_INFO("PipeC fused off\n"); > info->num_pipes -= 1; > } > - } else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) { > + } else if (HAS_DISPLAY(dev_priv) && (INTEL_GEN(dev_priv) >= 9)) { ^ ^
Drop the pointless parens please. Otherwise seems good. > u32 dfsm = I915_READ(SKL_DFSM); > u8 disabled_mask = 0; > bool invalid; > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
