On Mon, Nov 19, 2018 at 04:41:07PM +0200, Imre Deak wrote: > Depending on the transcoder enum values to translate from transcoder > to pipe/transcoder register addresses can easily break if we add a new > transcoder. So remove the dependency by using named initializers. > > Suggested-by: Ville Syrjälä <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Signed-off-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/i915_pci.c | 52 > ++++++++++++++++++++++++++++++----------- > 1 file changed, 38 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 983ae7fd8217..1b81d7cb209e 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -33,16 +33,30 @@ > #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) > > #define GEN_DEFAULT_PIPEOFFSETS \ > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ > - PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ > - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET } > + .pipe_offsets = { \ > + [TRANSCODER_A] = PIPE_A_OFFSET, \ > + [TRANSCODER_B] = PIPE_B_OFFSET, \ > + [TRANSCODER_C] = PIPE_C_OFFSET, \ > + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
Hmm. We do define this as int pipe_offsets[I915_MAX_TRANSCODERS], and PIPECONF/TRANSCONF is per-transcoder so I suppose using TRANSCODER_foo here make sense. Couple of things that came to mind while thinking about this: - pipe_offsets[] & co. could probably be u32 since we don't need negative values - _PIPE_EDP could be removed, which would maybe shrink a few arrays based on I915_MAX_PIPES Patch is Reviewed-by: Ville Syrjälä <[email protected]> > + }, \ > + .trans_offsets = { \ > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ > + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ > + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ > + } > > #define GEN_CHV_PIPEOFFSETS \ > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ > - CHV_PIPE_C_OFFSET }, \ > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ > - CHV_TRANSCODER_C_OFFSET } > + .pipe_offsets = { \ > + [TRANSCODER_A] = PIPE_A_OFFSET, \ > + [TRANSCODER_B] = PIPE_B_OFFSET, \ > + [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ > + }, \ > + .trans_offsets = { \ > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ > + [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ > + } > > #define CURSOR_OFFSETS \ > .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, > CHV_CURSOR_C_OFFSET } > @@ -592,12 +606,22 @@ static const struct intel_device_info > intel_cannonlake_info = { > > #define GEN11_FEATURES \ > GEN10_FEATURES, \ > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ > - PIPE_C_OFFSET, PIPE_EDP_OFFSET, \ > - PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \ > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ > - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \ > - TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \ > + .pipe_offsets = { \ > + [TRANSCODER_A] = PIPE_A_OFFSET, \ > + [TRANSCODER_B] = PIPE_B_OFFSET, \ > + [TRANSCODER_C] = PIPE_C_OFFSET, \ > + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ > + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ > + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ > + }, \ > + .trans_offsets = { \ > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ > + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ > + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ > + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ > + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ > + }, \ > GEN(11), \ > .ddb_size = 2048, \ > .has_logical_ring_elsq = 1 > -- > 2.13.2 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
