On Tue, 13 Nov 2018, Jani Nikula <[email protected]> wrote: > On Mon, 12 Nov 2018, Tvrtko Ursulin <[email protected]> wrote: >> From: Tvrtko Ursulin <[email protected]> >> >> Now that we are down to one caller, which does not even modify copied >> device info, we can remove the mkwrite_device_info helper and convert the >> device info pointer itself to be a pointer to static table instead of a >> copy. >> >> Only unfortnate thing is that we need to convert all callsites which were >> referencing the device info directly to using the INTEL_INFO helper. > > I'm not sure if that's all that bad. When I was toying around with > mkwrite_device_info removal, I actually started off with changing all > device info references to INTEL_INFO. It's a big patch, but it nicely > centralizes many of the other changes instead of splattering all over > the place. > > I'd actually like to see RUNTIME_INFO or similar macro as well, just to > be able to change the way it's handled later on.
Oh, and it would actually be possible to start off with a RUNTIME_INFO macro that's just INTEL_INFO, and change all use sites of runtime info first. Everything still pointing at the same place. Could then proceed with a runtime copy, and then with actual splitting off of the structs. Just food for thought, and definitely not a request to restructure the series. But it might simplify some of the steps. BR, Jani. > > BR, > Jani. > > >> >> Signed-off-by: Tvrtko Ursulin <[email protected]> >> Cc: Chris Wilson <[email protected]> >> Cc: Jani Nikula <[email protected]> >> --- >> drivers/gpu/drm/i915/i915_drv.c | 9 +- >> drivers/gpu/drm/i915/i915_drv.h | 107 ++++++------- >> drivers/gpu/drm/i915/i915_reg.h | 190 +++++++++++------------ >> drivers/gpu/drm/i915/intel_device_info.c | 11 +- >> drivers/gpu/drm/i915/intel_device_info.h | 2 +- >> drivers/gpu/drm/i915/intel_uncore.c | 2 +- >> 6 files changed, 151 insertions(+), 170 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c >> b/drivers/gpu/drm/i915/i915_drv.c >> index bbdd36119eae..77dd7763b334 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -1620,7 +1620,7 @@ static void i915_welcome_messages(struct >> drm_i915_private *dev_priv) >> if (drm_debug & DRM_UT_DRIVER) { >> struct drm_printer p = drm_debug_printer("i915 device info:"); >> >> - intel_device_info_dump(&dev_priv->info, &p); >> + intel_device_info_dump(dev_priv, &p); >> intel_device_info_dump_runtime(&dev_priv->runtime_info, &p); >> } >> >> @@ -1638,7 +1638,7 @@ i915_driver_create(struct pci_dev *pdev, const struct >> pci_device_id *ent) >> const struct intel_device_info *match_info = >> (struct intel_device_info *)ent->driver_data; >> struct intel_runtime_device_info *runtime_info; >> - struct intel_device_info *device_info; >> + const struct intel_device_info *device_info; >> struct drm_i915_private *i915; >> int err; >> >> @@ -1654,12 +1654,9 @@ i915_driver_create(struct pci_dev *pdev, const struct >> pci_device_id *ent) >> >> i915->drm.pdev = pdev; >> i915->drm.dev_private = i915; >> + i915->info = device_info = match_info; >> pci_set_drvdata(pdev, &i915->drm); >> >> - /* Setup the write-once "constant" device info */ >> - device_info = mkwrite_device_info(i915); >> - memcpy(device_info, match_info, sizeof(*device_info)); >> - >> BUILD_BUG_ON(INTEL_MAX_PLATFORMS > >> BITS_PER_TYPE(device_info->platform_mask)); >> BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask)); >> diff --git a/drivers/gpu/drm/i915/i915_drv.h >> b/drivers/gpu/drm/i915/i915_drv.h >> index 4fabbcd6cfb2..77ef41d53558 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -1588,7 +1588,7 @@ struct drm_i915_private { >> struct kmem_cache *dependencies; >> struct kmem_cache *priorities; >> >> - const struct intel_device_info info; >> + const struct intel_device_info *info; >> struct intel_runtime_device_info runtime_info; >> struct intel_driver_caps caps; >> >> @@ -2349,13 +2349,7 @@ static inline unsigned int i915_sg_segment_size(void) >> return size; >> } >> >> -static inline const struct intel_device_info * >> -intel_info(const struct drm_i915_private *dev_priv) >> -{ >> - return &dev_priv->info; >> -} >> - >> -#define INTEL_INFO(dev_priv) intel_info((dev_priv)) >> +#define INTEL_INFO(dev_priv) ((dev_priv)->info) >> #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) >> >> #define INTEL_GEN(dev_priv) ((dev_priv)->runtime_info.gen) >> @@ -2371,7 +2365,7 @@ intel_info(const struct drm_i915_private *dev_priv) >> >> /* Returns true if Gen is in inclusive range [Start, End] */ >> #define IS_GEN(dev_priv, s, e) \ >> - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) >> + (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) >> >> /* >> * Return true if revision is in range [since,until] inclusive. >> @@ -2381,7 +2375,7 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define IS_REVID(p, since, until) \ >> (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) >> >> -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) >> +#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & >> BIT(p)) >> >> #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) >> #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) >> @@ -2403,7 +2397,7 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) >> #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) >> #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ >> - (dev_priv)->info.gt == 1) >> + INTEL_INFO(dev_priv)->gt == 1) >> #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) >> #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) >> #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) >> @@ -2415,7 +2409,7 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) >> #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) >> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) >> -#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) >> +#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) >> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ >> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) >> #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ >> @@ -2426,11 +2420,11 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ >> (INTEL_DEVID(dev_priv) & 0xf) == 0xe) >> #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ >> - (dev_priv)->info.gt == 3) >> + INTEL_INFO(dev_priv)->gt == 3) >> #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ >> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) >> #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ >> - (dev_priv)->info.gt == 3) >> + INTEL_INFO(dev_priv)->gt == 3) >> /* ULX machines are also considered ULT. */ >> #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ >> INTEL_DEVID(dev_priv) == 0x0A1E) >> @@ -2453,21 +2447,21 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \ >> INTEL_DEVID(dev_priv) == 0x87C0) >> #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ >> - (dev_priv)->info.gt == 2) >> + INTEL_INFO(dev_priv)->gt == 2) >> #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ >> - (dev_priv)->info.gt == 3) >> + INTEL_INFO(dev_priv)->gt == 3) >> #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ >> - (dev_priv)->info.gt == 4) >> + INTEL_INFO(dev_priv)->gt == 4) >> #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ >> - (dev_priv)->info.gt == 2) >> + INTEL_INFO(dev_priv)->gt == 2) >> #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ >> - (dev_priv)->info.gt == 3) >> + INTEL_INFO(dev_priv)->gt == 3) >> #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ >> (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) >> #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ >> - (dev_priv)->info.gt == 2) >> + INTEL_INFO(dev_priv)->gt == 2) >> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ >> - (dev_priv)->info.gt == 3) >> + INTEL_INFO(dev_priv)->gt == 3) >> #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ >> (INTEL_DEVID(dev_priv) & 0x0004) == >> 0x0004) >> >> @@ -2530,16 +2524,16 @@ intel_info(const struct drm_i915_private *dev_priv) >> * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for >> particular >> * chips, etc.). >> */ >> -#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) >> -#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) >> -#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) >> -#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) >> -#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) >> -#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) >> -#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) >> -#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) >> -#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) >> -#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) >> +#define IS_GEN2(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(1))) >> +#define IS_GEN3(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(2))) >> +#define IS_GEN4(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(3))) >> +#define IS_GEN5(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(4))) >> +#define IS_GEN6(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(5))) >> +#define IS_GEN7(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(6))) >> +#define IS_GEN8(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(7))) >> +#define IS_GEN9(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(8))) >> +#define IS_GEN10(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(9))) >> +#define IS_GEN11(dev_priv) (!!(INTEL_INFO(dev_priv)->gen_mask & BIT(10))) >> >> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) >> #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) >> @@ -2566,20 +2560,20 @@ intel_info(const struct drm_i915_private *dev_priv) >> >> #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) >> >> -#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) >> -#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) >> +#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) >> +#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) >> #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) >> #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ >> IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) >> >> -#define HWS_NEEDS_PHYSICAL(dev_priv) >> ((dev_priv)->info.hws_needs_physical) >> +#define HWS_NEEDS_PHYSICAL(dev_priv) >> (INTEL_INFO(dev_priv)->hws_needs_physical) >> >> #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ >> - ((dev_priv)->info.has_logical_ring_contexts) >> + (INTEL_INFO(dev_priv)->has_logical_ring_contexts) >> #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ >> - ((dev_priv)->info.has_logical_ring_elsq) >> + (INTEL_INFO(dev_priv)->has_logical_ring_elsq) >> #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ >> - ((dev_priv)->info.has_logical_ring_preemption) >> + (INTEL_INFO(dev_priv)->has_logical_ring_preemption) >> >> #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) >> >> @@ -2596,9 +2590,9 @@ intel_info(const struct drm_i915_private *dev_priv) >> ((sizes) & ~(dev_priv)->runtime_info.page_sizes) == 0; \ >> }) >> >> -#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) >> +#define HAS_OVERLAY(dev_priv) >> (INTEL_INFO(dev_priv)->has_overlay) >> #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ >> - ((dev_priv)->info.overlay_needs_physical) >> + (INTEL_INFO(dev_priv)->overlay_needs_physical) >> >> /* Early gen2 have a totally busted CS tlb and require pinned batches. */ >> #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || >> IS_I845G(dev_priv)) >> @@ -2619,8 +2613,8 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ >> !(IS_I915G(dev_priv) || \ >> IS_I915GM(dev_priv))) >> -#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) >> -#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) >> +#define SUPPORTS_TV(dev_priv) >> (INTEL_INFO(dev_priv)->supports_tv) >> +#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->has_hotplug) >> >> #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) >> #define HAS_FBC(dev_priv) ((dev_priv)->runtime_info.has_fbc) >> @@ -2628,30 +2622,30 @@ intel_info(const struct drm_i915_private *dev_priv) >> >> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) >> >> -#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) >> +#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->has_dp_mst) >> >> -#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) >> -#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) >> -#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) >> +#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->has_ddi) >> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) >> (INTEL_INFO(dev_priv)->has_fpga_dbg) >> +#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->has_psr) >> >> #define HAS_RC6(dev_priv) ((dev_priv)->runtime_info.has_rc6) >> #define HAS_RC6p(dev_priv) ((dev_priv)->runtime_info.has_rc6p) >> #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ >> >> -#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) >> +#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->has_csr) >> >> -#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) >> -#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) >> +#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) >> +#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) >> >> -#define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc) >> +#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->has_ipc) >> >> /* >> * For now, anything with a GuC requires uCode loading, and then supports >> * command submission once loaded. But these are logically independent >> * properties, so we have separate macros to test them. >> */ >> -#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) >> -#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) >> +#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc) >> +#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct) >> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) >> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) >> >> @@ -2704,12 +2698,12 @@ intel_info(const struct drm_i915_private *dev_priv) >> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) >> #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) >> >> -#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) >> +#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->has_gmch_display) >> >> #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) >> >> /* DPF == dynamic parity feature */ >> -#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) >> +#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) >> #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ >> 2 : HAS_L3_DPF(dev_priv)) >> >> @@ -3465,13 +3459,6 @@ static inline void intel_register_dsm_handler(void) { >> return; } >> static inline void intel_unregister_dsm_handler(void) { return; } >> #endif /* CONFIG_ACPI */ >> >> -/* intel_device_info.c */ >> -static inline struct intel_device_info * >> -mkwrite_device_info(struct drm_i915_private *dev_priv) >> -{ >> - return (struct intel_device_info *)&dev_priv->info; >> -} >> - >> /* modesetting */ >> extern void intel_modeset_init_hw(struct drm_device *dev); >> extern int intel_modeset_init(struct drm_device *dev); >> diff --git a/drivers/gpu/drm/i915/i915_reg.h >> b/drivers/gpu/drm/i915/i915_reg.h >> index fe4b913e46ac..4c0e5b62e7fa 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -179,15 +179,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) >> * Device info offset array based helpers for groups of registers with >> unevenly >> * spaced base offsets. >> */ >> -#define _MMIO_PIPE2(pipe, reg) >> _MMIO(dev_priv->info.pipe_offsets[pipe] - \ >> - >> dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ >> - >> dev_priv->info.display_mmio_offset) >> -#define _MMIO_TRANS2(pipe, reg) >> _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ >> - >> dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ >> - >> dev_priv->info.display_mmio_offset) >> -#define _CURSOR2(pipe, reg) >> _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ >> - >> dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ >> - >> dev_priv->info.display_mmio_offset) >> +#define _MMIO_PIPE2(pipe, reg) >> _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ >> + >> INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ >> + >> INTEL_INFO(dev_priv)->display_mmio_offset) >> +#define _MMIO_TRANS2(pipe, reg) >> _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \ >> + >> INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ >> + >> INTEL_INFO(dev_priv)->display_mmio_offset) >> +#define _CURSOR2(pipe, reg) >> _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ >> + >> INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ >> + >> INTEL_INFO(dev_priv)->display_mmio_offset) >> >> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) >> #define _MASKED_FIELD(mask, value) ({ >> \ >> @@ -3153,9 +3153,9 @@ enum i915_power_well_id { >> /* >> * Clock control & power management >> */ >> -#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) >> -#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) >> -#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) >> +#define _DPLL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6014) >> +#define _DPLL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6018) >> +#define _CHV_DPLL_C (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6030) >> #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) >> >> #define VGA0 _MMIO(0x6000) >> @@ -3252,9 +3252,9 @@ enum i915_power_well_id { >> #define SDVO_MULTIPLIER_SHIFT_HIRES 4 >> #define SDVO_MULTIPLIER_SHIFT_VGA 0 >> >> -#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) >> -#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) >> -#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) >> +#define _DPLL_A_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x601c) >> +#define _DPLL_B_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6020) >> +#define _CHV_DPLL_C_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x603c) >> #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, >> _CHV_DPLL_C_MD) >> >> /* >> @@ -3326,7 +3326,7 @@ enum i915_power_well_id { >> #define DSTATE_PLL_D3_OFF (1 << 3) >> #define DSTATE_GFX_CLOCK_GATING (1 << 1) >> #define DSTATE_DOT_CLOCK_GATING (1 << 0) >> -#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + >> 0x6200) >> +#define DSPCLK_GATE_D _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + 0x6200) >> # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ >> # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ >> # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ >> @@ -3466,7 +3466,7 @@ enum i915_power_well_id { >> #define _PALETTE_A 0xa000 >> #define _PALETTE_B 0xa800 >> #define _CHV_PALETTE_C 0xc000 >> -#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \ >> +#define PALETTE(pipe, i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + \ >> _PICK((pipe), _PALETTE_A, \ >> _PALETTE_B, _CHV_PALETTE_C) + \ >> (i) * 4) >> @@ -4295,7 +4295,7 @@ enum { >> >> >> /* Hotplug control (945+ only) */ >> -#define PORT_HOTPLUG_EN >> _MMIO(dev_priv->info.display_mmio_offset + 0x61110) >> +#define PORT_HOTPLUG_EN >> _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61110) >> #define PORTB_HOTPLUG_INT_EN (1 << 29) >> #define PORTC_HOTPLUG_INT_EN (1 << 28) >> #define PORTD_HOTPLUG_INT_EN (1 << 27) >> @@ -4325,7 +4325,7 @@ enum { >> #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) >> #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) >> >> -#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + >> 0x61114) >> +#define PORT_HOTPLUG_STAT _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + 0x61114) >> /* >> * HDMI/DP bits are g4x+ >> * >> @@ -4407,7 +4407,7 @@ enum { >> >> #define PORT_DFT_I9XX _MMIO(0x61150) >> #define DC_BALANCE_RESET (1 << 25) >> -#define PORT_DFT2_G4X >> _MMIO(dev_priv->info.display_mmio_offset + 0x61154) >> +#define PORT_DFT2_G4X >> _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61154) >> #define DC_BALANCE_RESET_VLV (1 << 31) >> #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) >> #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ >> @@ -4680,7 +4680,7 @@ enum { >> #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 >> >> /* Panel fitting */ >> -#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + >> 0x61230) >> +#define PFIT_CONTROL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + 0x61230) >> #define PFIT_ENABLE (1 << 31) >> #define PFIT_PIPE_MASK (3 << 29) >> #define PFIT_PIPE_SHIFT 29 >> @@ -4698,7 +4698,7 @@ enum { >> #define PFIT_SCALING_PROGRAMMED (1 << 26) >> #define PFIT_SCALING_PILLAR (2 << 26) >> #define PFIT_SCALING_LETTER (3 << 26) >> -#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) >> +#define PFIT_PGM_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61234) >> /* Pre-965 */ >> #define PFIT_VERT_SCALE_SHIFT 20 >> #define PFIT_VERT_SCALE_MASK 0xfff00000 >> @@ -4710,25 +4710,25 @@ enum { >> #define PFIT_HORIZ_SCALE_SHIFT_965 0 >> #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff >> >> -#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) >> +#define PFIT_AUTO_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61238) >> >> -#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) >> -#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) >> +#define _VLV_BLC_PWM_CTL2_A (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61250) >> +#define _VLV_BLC_PWM_CTL2_B (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61350) >> #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ >> _VLV_BLC_PWM_CTL2_B) >> >> -#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) >> -#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) >> +#define _VLV_BLC_PWM_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61254) >> +#define _VLV_BLC_PWM_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61354) >> #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ >> _VLV_BLC_PWM_CTL_B) >> >> -#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) >> -#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) >> +#define _VLV_BLC_HIST_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61260) >> +#define _VLV_BLC_HIST_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61360) >> #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ >> _VLV_BLC_HIST_CTL_B) >> >> /* Backlight control */ >> -#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + >> 0x61250) /* 965+ only */ >> +#define BLC_PWM_CTL2 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + 0x61250) /* 965+ only */ >> #define BLM_PWM_ENABLE (1 << 31) >> #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ >> #define BLM_PIPE_SELECT (1 << 29) >> @@ -4751,7 +4751,7 @@ enum { >> #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) >> #define BLM_PHASE_IN_INCR_SHIFT (0) >> #define BLM_PHASE_IN_INCR_MASK (0xff << 0) >> -#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) >> +#define BLC_PWM_CTL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x61254) >> /* >> * This is the most significant 15 bits of the number of backlight cycles >> in a >> * complete cycle of the modulated backlight control. >> @@ -4773,7 +4773,7 @@ enum { >> #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) >> #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ >> >> -#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + >> 0x61260) >> +#define BLC_HIST_CTL _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + 0x61260) >> #define BLM_HISTOGRAM_ENABLE (1 << 31) >> >> /* New registers for PCH-split platforms. Safe where new bits show up, the >> @@ -5397,47 +5397,47 @@ enum { >> * is 20 bytes in each direction, hence the 5 fixed >> * data registers >> */ >> -#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + >> 0x64010) >> -#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) >> -#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) >> -#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) >> -#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) >> -#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) >> - >> -#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + >> 0x64110) >> -#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) >> -#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) >> -#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) >> -#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) >> -#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) >> - >> -#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + >> 0x64210) >> -#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) >> -#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) >> -#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) >> -#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) >> -#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) >> - >> -#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + >> 0x64310) >> -#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) >> -#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) >> -#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) >> -#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) >> -#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) >> - >> -#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + >> 0x64410) >> -#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414) >> -#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418) >> -#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c) >> -#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420) >> -#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424) >> - >> -#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + >> 0x64510) >> -#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514) >> -#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518) >> -#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c) >> -#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520) >> -#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524) >> +#define _DPA_AUX_CH_CTL >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64010) >> +#define _DPA_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64014) >> +#define _DPA_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64018) >> +#define _DPA_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x6401c) >> +#define _DPA_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64020) >> +#define _DPA_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64024) >> + >> +#define _DPB_AUX_CH_CTL >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64110) >> +#define _DPB_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64114) >> +#define _DPB_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64118) >> +#define _DPB_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x6411c) >> +#define _DPB_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64120) >> +#define _DPB_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64124) >> + >> +#define _DPC_AUX_CH_CTL >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64210) >> +#define _DPC_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64214) >> +#define _DPC_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64218) >> +#define _DPC_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x6421c) >> +#define _DPC_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64220) >> +#define _DPC_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64224) >> + >> +#define _DPD_AUX_CH_CTL >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64310) >> +#define _DPD_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64314) >> +#define _DPD_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64318) >> +#define _DPD_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x6431c) >> +#define _DPD_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64320) >> +#define _DPD_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64324) >> + >> +#define _DPE_AUX_CH_CTL >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64410) >> +#define _DPE_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64414) >> +#define _DPE_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64418) >> +#define _DPE_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x6441c) >> +#define _DPE_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64420) >> +#define _DPE_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64424) >> + >> +#define _DPF_AUX_CH_CTL >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x64510) >> +#define _DPF_AUX_CH_DATA1 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64514) >> +#define _DPF_AUX_CH_DATA2 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64518) >> +#define _DPF_AUX_CH_DATA3 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x6451c) >> +#define _DPF_AUX_CH_DATA4 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64520) >> +#define _DPF_AUX_CH_DATA5 (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x64524) >> >> #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, >> _DPB_AUX_CH_CTL) >> #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, >> _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ >> @@ -5713,7 +5713,7 @@ enum { >> #define DPINVGTT_STATUS_MASK 0xff >> #define DPINVGTT_STATUS_MASK_CHV 0xfff >> >> -#define DSPARB >> _MMIO(dev_priv->info.display_mmio_offset + 0x70030) >> +#define DSPARB >> _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70030) >> #define DSPARB_CSTART_MASK (0x7f << 7) >> #define DSPARB_CSTART_SHIFT 7 >> #define DSPARB_BSTART_MASK (0x7f) >> @@ -5748,7 +5748,7 @@ enum { >> #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) >> >> /* pnv/gen4/g4x/vlv/chv */ >> -#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + >> 0x70034) >> +#define DSPFW1 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + 0x70034) >> #define DSPFW_SR_SHIFT 23 >> #define DSPFW_SR_MASK (0x1ff << 23) >> #define DSPFW_CURSORB_SHIFT 16 >> @@ -5759,7 +5759,7 @@ enum { >> #define DSPFW_PLANEA_SHIFT 0 >> #define DSPFW_PLANEA_MASK (0x7f << 0) >> #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ >> -#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + >> 0x70038) >> +#define DSPFW2 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + 0x70038) >> #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ >> #define DSPFW_FBC_SR_SHIFT 28 >> #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ >> @@ -5775,7 +5775,7 @@ enum { >> #define DSPFW_SPRITEA_SHIFT 0 >> #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ >> #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ >> -#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + >> 0x7003c) >> +#define DSPFW3 _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset >> + 0x7003c) >> #define DSPFW_HPLL_SR_EN (1 << 31) >> #define PINEVIEW_SELF_REFRESH_EN (1 << 30) >> #define DSPFW_CURSOR_SR_SHIFT 24 >> @@ -6191,35 +6191,35 @@ enum { >> * [10:1f] all >> * [30:32] all >> */ >> -#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + >> (i) * 4) >> -#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + >> (i) * 4) >> -#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + >> (i) * 4) >> +#define SWF0(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x70410 + (i) * 4) >> +#define SWF1(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71410 + (i) * 4) >> +#define SWF3(i) _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x72414 + (i) * 4) >> #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) >> >> /* Pipe B */ >> -#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) >> -#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) >> -#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) >> +#define _PIPEBDSL (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71000) >> +#define _PIPEBCONF (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71008) >> +#define _PIPEBSTAT (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71024) >> #define _PIPEBFRAMEHIGH 0x71040 >> #define _PIPEBFRAMEPIXEL 0x71044 >> -#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) >> -#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + >> 0x71044) >> +#define _PIPEB_FRMCOUNT_G4X (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71040) >> +#define _PIPEB_FLIPCOUNT_G4X >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x71044) >> >> >> /* Display B control */ >> -#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) >> +#define _DSPBCNTR (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71180) >> #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) >> #define DISPPLANE_ALPHA_TRANS_DISABLE 0 >> #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 >> #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) >> -#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) >> -#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) >> -#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) >> -#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) >> -#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) >> -#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + >> 0x711A4) >> -#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) >> -#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + >> 0x711AC) >> +#define _DSPBADDR (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71184) >> +#define _DSPBSTRIDE (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71188) >> +#define _DSPBPOS (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x7118C) >> +#define _DSPBSIZE (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x71190) >> +#define _DSPBSURF (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x7119C) >> +#define _DSPBTILEOFF >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4) >> +#define _DSPBOFFSET (INTEL_INFO(dev_priv)->display_mmio_offset + >> 0x711A4) >> +#define _DSPBSURFLIVE >> (INTEL_INFO(dev_priv)->display_mmio_offset + 0x711AC) >> >> /* ICL DSI 0 and 1 */ >> #define _PIPEDSI0CONF 0x7b008 >> @@ -8773,7 +8773,7 @@ enum { >> #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2) >> >> /* Audio */ >> -#define G4X_AUD_VID_DID >> _MMIO(dev_priv->info.display_mmio_offset + 0x62020) >> +#define G4X_AUD_VID_DID >> _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x62020) >> #define INTEL_AUDIO_DEVCL 0x808629FB >> #define INTEL_AUDIO_DEVBLC 0x80862801 >> #define INTEL_AUDIO_DEVCTG 0x80862802 >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c >> b/drivers/gpu/drm/i915/intel_device_info.c >> index aeb7b9225b18..00758d11047b 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.c >> +++ b/drivers/gpu/drm/i915/intel_device_info.c >> @@ -121,19 +121,16 @@ intel_device_info_dump_runtime(const struct >> intel_runtime_device_info *info, >> intel_runtime_device_info_dump_flags(info, p); >> } >> >> -void intel_device_info_dump(const struct intel_device_info *info, >> +void intel_device_info_dump(struct drm_i915_private *dev_priv, >> struct drm_printer *p) >> { >> - struct drm_i915_private *dev_priv = >> - container_of(info, struct drm_i915_private, info); >> - >> drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", >> INTEL_DEVID(dev_priv), >> INTEL_REVID(dev_priv), >> - intel_platform_name(info->platform), >> - info->__gen); >> + intel_platform_name(INTEL_INFO(dev_priv)->platform), >> + INTEL_INFO(dev_priv)->__gen); >> >> - intel_device_info_dump_flags(info, p); >> + intel_device_info_dump_flags(INTEL_INFO(dev_priv), p); >> } >> >> void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h >> b/drivers/gpu/drm/i915/intel_device_info.h >> index 50c8fda20bdd..9bacd466f4a2 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.h >> +++ b/drivers/gpu/drm/i915/intel_device_info.h >> @@ -270,7 +270,7 @@ static inline void sseu_set_eus(struct sseu_dev_info >> *sseu, >> const char *intel_platform_name(enum intel_platform platform); >> >> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); >> -void intel_device_info_dump(const struct intel_device_info *info, >> +void intel_device_info_dump(struct drm_i915_private *dev_priv, >> struct drm_printer *p); >> void intel_device_info_dump_flags(const struct intel_device_info *info, >> struct drm_printer *p); >> diff --git a/drivers/gpu/drm/i915/intel_uncore.c >> b/drivers/gpu/drm/i915/intel_uncore.c >> index 9289515108c3..def498402bbb 100644 >> --- a/drivers/gpu/drm/i915/intel_uncore.c >> +++ b/drivers/gpu/drm/i915/intel_uncore.c >> @@ -2256,7 +2256,7 @@ bool intel_has_gpu_reset(struct drm_i915_private >> *dev_priv) >> >> bool intel_has_reset_engine(struct drm_i915_private *dev_priv) >> { >> - return (dev_priv->info.has_reset_engine && >> + return (INTEL_INFO(dev_priv)->has_reset_engine && >> i915_modparams.reset >= 2); >> } -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
