On Tue, 2 Oct 2018 at 15:07, Mika Kuoppala <[email protected]> wrote: > > All other master control register bits, except the enable, > are read only and they are level indications of the second > level interrupt status. Only touch enable bit and rectify > the comment. > > Cc: Chris Wilson <[email protected]> > Cc: Dhinakaran Pandiyan <[email protected]> > Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Matthew Auld <[email protected]> _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
- [Intel-gfx] [PATCH 1/4] drm/i915/gen8: Disable master intr b... Mika Kuoppala
- [Intel-gfx] [PATCH 3/4] drm/i915/icl: Disable master in... Mika Kuoppala
- [Intel-gfx] [PATCH 4/4] drm/i915/icl: Handle GT interru... Mika Kuoppala
- Re: [Intel-gfx] [PATCH 4/4] drm/i915/icl: Handle GT... Chris Wilson
- Re: [Intel-gfx] [PATCH 4/4] drm/i915/icl: Handl... Mika Kuoppala
- Re: [Intel-gfx] [PATCH 4/4] drm/i915/icl: H... Chris Wilson
- [Intel-gfx] [PATCH 2/4] drm/i915/icl: No need to ack in... Mika Kuoppala
- Re: [Intel-gfx] [PATCH 2/4] drm/i915/icl: No need t... Matthew Auld
- [Intel-gfx] ✓ Fi.CI.BAT: success for series starting wi... Patchwork
- Re: [Intel-gfx] [PATCH 1/4] drm/i915/gen8: Disable mast... Chris Wilson
- [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting wi... Patchwork
