On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > We can easily calculate the plane can_scale/min_downscale on demand. > And later on we'll probably want to start calculating these > dynamically > based on the cdclk just as skl already does.
Reviewed-by: José Roberto de Souza <[email protected]> > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 8 +------- > drivers/gpu/drm/i915/intel_drv.h | 2 -- > drivers/gpu/drm/i915/intel_sprite.c | 38 ++++++++++++------------ > ------------ > 3 files changed, 13 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index bc2a712311ba..fdc5bedc5135 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -13708,12 +13708,8 @@ intel_primary_plane_create(struct > drm_i915_private *dev_priv, enum pipe pipe) > > primary->base.state = &state->base; > > - primary->can_scale = false; > - primary->max_downscale = 1; > - if (INTEL_GEN(dev_priv) >= 9) { > - primary->can_scale = true; > + if (INTEL_GEN(dev_priv) >= 9) > state->scaler_id = -1; > - } > primary->pipe = pipe; > /* > * On gen2/3 only plane A can do FBC, but the panel fitter and > LVDS > @@ -13881,8 +13877,6 @@ intel_cursor_plane_create(struct > drm_i915_private *dev_priv, > > cursor->base.state = &state->base; > > - cursor->can_scale = false; > - cursor->max_downscale = 1; > cursor->pipe = pipe; > cursor->i9xx_plane = (enum i9xx_plane_id) pipe; > cursor->id = PLANE_CURSOR; > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index cc381f680338..c6c782e14897 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -950,10 +950,8 @@ struct intel_plane { > enum i9xx_plane_id i9xx_plane; > enum plane_id id; > enum pipe pipe; > - bool can_scale; > bool has_fbc; > bool has_ccs; > - int max_downscale; > uint32_t frontbuffer_bit; > > struct { > diff --git a/drivers/gpu/drm/i915/intel_sprite.c > b/drivers/gpu/drm/i915/intel_sprite.c > index a07d951afbf9..0d3931b8a981 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -765,7 +765,7 @@ ivb_update_plane(struct intel_plane *plane, > I915_WRITE_FW(SPRLINOFF(pipe), linear_offset); > > I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); > - if (plane->can_scale) > + if (IS_IVYBRIDGE(dev_priv)) > I915_WRITE_FW(SPRSCALE(pipe), sprscale); > I915_WRITE_FW(SPRCTL(pipe), sprctl); > I915_WRITE_FW(SPRSURF(pipe), > @@ -786,7 +786,7 @@ ivb_disable_plane(struct intel_plane *plane, > struct intel_crtc *crtc) > > I915_WRITE_FW(SPRCTL(pipe), 0); > /* Can't leave the scaler enabled... */ > - if (plane->can_scale) > + if (IS_IVYBRIDGE(dev_priv)) > I915_WRITE_FW(SPRSCALE(pipe), 0); > > I915_WRITE_FW(SPRSURF(pipe), 0); > @@ -991,7 +991,6 @@ intel_check_sprite_plane(struct intel_plane > *plane, > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > struct drm_framebuffer *fb = state->base.fb; > int max_scale, min_scale; > - bool can_scale; > int ret; > uint32_t pixel_format = 0; > > @@ -1014,25 +1013,29 @@ intel_check_sprite_plane(struct intel_plane > *plane, > return -EINVAL; > } > > - /* setup can_scale, min_scale, max_scale */ > if (INTEL_GEN(dev_priv) >= 9) { > if (state->base.fb) > pixel_format = state->base.fb->format->format; > /* use scaler when colorkey is not required */ > if (!state->ckey.flags) { > - can_scale = 1; > min_scale = 1; > max_scale = > skl_max_scale(crtc, crtc_state, > pixel_format); > } else { > - can_scale = 0; > min_scale = DRM_PLANE_HELPER_NO_SCALING; > max_scale = DRM_PLANE_HELPER_NO_SCALING; > } > } else { > - can_scale = plane->can_scale; > - max_scale = plane->max_downscale << 16; > - min_scale = plane->can_scale ? 1 : (1 << 16); > + if (INTEL_GEN(dev_priv) < 7) { > + min_scale = 1; > + max_scale = 16 << 16; > + } else if (IS_IVYBRIDGE(dev_priv)) { > + min_scale = 1; > + max_scale = 2 << 16; > + } else { > + min_scale = DRM_PLANE_HELPER_NO_SCALING; > + max_scale = DRM_PLANE_HELPER_NO_SCALING; > + } > } > > ret = drm_atomic_helper_check_plane_state(&state->base, > @@ -1078,8 +1081,6 @@ intel_check_sprite_plane(struct intel_plane > *plane, > unsigned int width_bytes; > int cpp = fb->format->cpp[0]; > > - WARN_ON(!can_scale); > - > width_bytes = ((src_x * cpp) & 63) + src_w * > cpp; > > /* FIXME interlacing min height is 6 */ > @@ -1549,7 +1550,6 @@ intel_sprite_plane_create(struct > drm_i915_private *dev_priv, > intel_plane->base.state = &state->base; > > if (INTEL_GEN(dev_priv) >= 9) { > - intel_plane->can_scale = true; > state->scaler_id = -1; > > intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, > pipe, > @@ -1576,9 +1576,6 @@ intel_sprite_plane_create(struct > drm_i915_private *dev_priv, > > plane_funcs = &skl_plane_funcs; > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > { > - intel_plane->can_scale = false; > - intel_plane->max_downscale = 1; > - > intel_plane->max_stride = i9xx_plane_max_stride; > intel_plane->update_plane = vlv_update_plane; > intel_plane->disable_plane = vlv_disable_plane; > @@ -1590,14 +1587,6 @@ intel_sprite_plane_create(struct > drm_i915_private *dev_priv, > > plane_funcs = &vlv_sprite_funcs; > } else if (INTEL_GEN(dev_priv) >= 7) { > - if (IS_IVYBRIDGE(dev_priv)) { > - intel_plane->can_scale = true; > - intel_plane->max_downscale = 2; > - } else { > - intel_plane->can_scale = false; > - intel_plane->max_downscale = 1; > - } > - > intel_plane->max_stride = g4x_sprite_max_stride; > intel_plane->update_plane = ivb_update_plane; > intel_plane->disable_plane = ivb_disable_plane; > @@ -1609,9 +1598,6 @@ intel_sprite_plane_create(struct > drm_i915_private *dev_priv, > > plane_funcs = &snb_sprite_funcs; > } else { > - intel_plane->can_scale = true; > - intel_plane->max_downscale = 16; > - > intel_plane->max_stride = g4x_sprite_max_stride; > intel_plane->update_plane = g4x_update_plane; > intel_plane->disable_plane = g4x_disable_plane; _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
