On Sat, 2018-07-21 at 10:11 +0100, Chris Wilson wrote: > Quoting Dhinakaran Pandiyan (2018-07-21 10:06:07) > > > > intel_tile_width_bytes() returns 128B for gen-2 y-tiled buffers > > while at > > the same time HAS_128_BYTE_Y_TILING() returns false for gen-2. I am > > assuming intel_tile_width_bytes() does the right thing. > > > > Cc: Chris Wilson <[email protected]> > > Cc: Ville Syrjälä <[email protected]> > > Signed-off-by: Dhinakaran Pandiyan <[email protected]> > It's rather that gen2 only has 128B tiling. Note that it only makes > any > difference for intel_tile_width_bytes()..
Okay, the macro is a bit misleading. Do you have any suggestions to clarify it or would you prefer I leave it as it is? > -Chris _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
