On Fri, 15 Jun 2018, Madhav Chauhan <[email protected]> wrote: > This patch adds the new registers and corresponding bit definitions > which will be used for programming/enable DSI PLL. > > Signed-off-by: Madhav Chauhan <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f0317bde..bf2d3e4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9339,6 +9339,18 @@ enum skl_power_gate { > #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) > #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF > > +#define _ICL_DSI_ESC_CLK_DIV0 0x6b090 > +#define _ICL_DSI_ESC_CLK_DIV1 0x6b890 > +#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ > + _ICL_DSI_ESC_CLK_DIV0, \ > + _ICL_DSI_ESC_CLK_DIV1) > +#define _ICL_DPHY_ESC_CLK_DIV0 0x162190 > +#define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 > +#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ > + _ICL_DPHY_ESC_CLK_DIV0, \ > + _ICL_DPHY_ESC_CLK_DIV1) > +#define ICL_ESC_CLK_DIV_MASK 0x1ff ^
Nitpick, 3 spaces there. With that fixed, Reviewed-by: Jani Nikula <[email protected]> Side note, you could define shifts and masks for both escape clock divider M and byte clocks per escape clock while at it. > + > /* Gen4+ Timestamp and Pipe Frame time stamp registers */ > #define GEN4_TIMESTAMP _MMIO(0x2358) > #define ILK_TIMESTAMP_HI _MMIO(0x70070) -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
