Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu: > From: Manasi Navare <[email protected]> > > DFLEXDPMLE register is required to tell the FIA hardware which > main links of DP are enabled on TCC Connectors. FIA uses this > information to program PHY to Controller signal mapping. > This register is applicable in both TC connector's Alternate mode > as well as DP connector mode. > > Cc: Jani Nikula <[email protected]> > Cc: Animesh Manna <[email protected]> > Cc: Madhav Chauhan <[email protected]> > Cc: Anusha Srivatsa <[email protected]> > Cc: Paulo Zanoni <[email protected]> > Signed-off-by: Manasi Navare <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index 28ce96ce0484..7f27fe2e38c7 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1990,6 +1990,11 @@ enum i915_power_well_id { > _ICL_PORT_COMP_DW > 10_A, \ > _ICL_PORT_COMP_DW > 10_B) > > +/* ICL PHY DFLEX registers */ > +#define ICL_PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
We can probably remove the ICL_ prefix since the register did not exist before. With or without that: Reviewed-by: Paulo Zanoni <[email protected]> Note: the patch that uses the register was removed from the series due to some problems identified. Will be upstreamed as soon as it's fixed. > +#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n))) > +#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n))) > + > /* BXT PHY Ref registers */ > #define _PORT_REF_DW3_A 0x16218C > #define _PORT_REF_DW3_BC 0x6C18C _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
