We never used this information on upper level. So let's just print the error and make the functions void.
Signed-off-by: Rodrigo Vivi <[email protected]> --- drivers/gpu/drm/i915/intel_drv.h | 4 ++-- drivers/gpu/drm/i915/intel_pm.c | 26 +++++++++++--------------- 2 files changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 0f733c5f0faf..2260aa1ecd8c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -2004,8 +2004,8 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv); void vlv_wm_sanitize(struct drm_i915_private *dev_priv); bool intel_can_enable_sagv(struct drm_atomic_state *state); u8 intel_sagv_block_time(const struct drm_i915_private *dev_priv); -int intel_enable_sagv(struct drm_i915_private *dev_priv); -int intel_disable_sagv(struct drm_i915_private *dev_priv); +void intel_enable_sagv(struct drm_i915_private *dev_priv); +void intel_disable_sagv(struct drm_i915_private *dev_priv); bool skl_wm_level_equals(const struct skl_wm_level *l1, const struct skl_wm_level *l2); bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 92a14cb7e674..2b6419b7bdd1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3606,16 +3606,15 @@ intel_has_sagv(struct drm_i915_private *dev_priv) * - All planes can enable watermarks for latencies >= SAGV engine block time * - We're not using an interlaced display configuration */ -int -intel_enable_sagv(struct drm_i915_private *dev_priv) +void intel_enable_sagv(struct drm_i915_private *dev_priv) { int ret; if (!intel_has_sagv(dev_priv)) - return 0; + return; if (dev_priv->sagv_status == I915_SAGV_ENABLED) - return 0; + return; DRM_DEBUG_KMS("Enabling the SAGV\n"); mutex_lock(&dev_priv->pcu_lock); @@ -3633,26 +3632,24 @@ intel_enable_sagv(struct drm_i915_private *dev_priv) if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; - return 0; + return; } else if (ret < 0) { - DRM_ERROR("Failed to enable the SAGV\n"); - return ret; + DRM_ERROR("Failed to enable the SAGV (%d)\n", ret); + return; } dev_priv->sagv_status = I915_SAGV_ENABLED; - return 0; } -int -intel_disable_sagv(struct drm_i915_private *dev_priv) +void intel_disable_sagv(struct drm_i915_private *dev_priv) { int ret; if (!intel_has_sagv(dev_priv)) - return 0; + return; if (dev_priv->sagv_status == I915_SAGV_DISABLED) - return 0; + return; DRM_DEBUG_KMS("Disabling the SAGV\n"); mutex_lock(&dev_priv->pcu_lock); @@ -3671,14 +3668,13 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; - return 0; + return; } else if (ret < 0) { DRM_ERROR("Failed to disable the SAGV (%d)\n", ret); - return ret; + return; } dev_priv->sagv_status = I915_SAGV_DISABLED; - return 0; } bool intel_can_enable_sagv(struct drm_atomic_state *state) -- 2.13.6 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
