These routines are identical except in the nature of the value parameter. For writes it is a pure in-param, but for a read, we need an out-param. Since they differ in a single line, merge the two routines into one.
Signed-off-by: Chris Wilson <[email protected]> --- drivers/gpu/drm/i915/intel_pm.c | 63 +++++++---------------------------------- 1 file changed, 10 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index cf8b4c28f1e1..c9636c684f65 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -9111,13 +9111,15 @@ static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv) } } -static int __sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) +static int __sandybridge_pcode_rw(struct drm_i915_private *dev_priv, + u32 mbox, u32 *val, bool is_read) { int status; lockdep_assert_held(&dev_priv->sb_lock); - /* GEN6_PCODE_* are outside of the forcewake domain, we can + /* + * GEN6_PCODE_* are outside of the forcewake domain, we can * use te fw I915_READ variants to reduce the amount of work * required when reading/writing. */ @@ -9140,7 +9142,8 @@ static int __sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, return -ETIMEDOUT; } - *val = I915_READ_FW(GEN6_PCODE_DATA); + if (is_read) + *val = I915_READ_FW(GEN6_PCODE_DATA); I915_WRITE_FW(GEN6_PCODE_DATA, 0); if (INTEL_GEN(dev_priv) > 6) @@ -9162,63 +9165,19 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val int status; mutex_lock(&dev_priv->sb_lock); - status = __sandybridge_pcode_read(dev_priv, mbox, val); + status = __sandybridge_pcode_rw(dev_priv, mbox, val, true); mutex_unlock(&dev_priv->sb_lock); return status; } -static int __sandybridge_pcode_write(struct drm_i915_private *dev_priv, - u32 mbox, u32 val) -{ - int status; - - /* GEN6_PCODE_* are outside of the forcewake domain, we can - * use te fw I915_READ variants to reduce the amount of work - * required when reading/writing. - */ - - if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { - DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n", - val, mbox, __builtin_return_address(0)); - return -EAGAIN; - } - - I915_WRITE_FW(GEN6_PCODE_DATA, val); - I915_WRITE_FW(GEN6_PCODE_DATA1, 0); - I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); - - if (__intel_wait_for_register_fw(dev_priv, - GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, - 500, 0, NULL)) { - DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n", - val, mbox, __builtin_return_address(0)); - return -ETIMEDOUT; - } - - I915_WRITE_FW(GEN6_PCODE_DATA, 0); - - if (INTEL_GEN(dev_priv) > 6) - status = gen7_check_mailbox_status(dev_priv); - else - status = gen6_check_mailbox_status(dev_priv); - - if (status) { - DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n", - val, mbox, __builtin_return_address(0), status); - return status; - } - - return 0; -} - int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) { int status; mutex_lock(&dev_priv->sb_lock); - status = __sandybridge_pcode_write(dev_priv, mbox, val); + status = __sandybridge_pcode_rw(dev_priv, mbox, &val, false); mutex_unlock(&dev_priv->sb_lock); return status; @@ -9228,11 +9187,9 @@ static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, u32 reply_mask, u32 reply, u32 *status) { - u32 val = request; - - *status = __sandybridge_pcode_read(dev_priv, mbox, &val); + *status = __sandybridge_pcode_rw(dev_priv, mbox, &request, true); - return *status || ((val & reply_mask) == reply); + return *status || ((request & reply_mask) == reply); } /** -- 2.15.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
