That fix was the disable render deptch cache pipeline flush
Signed-off-by: Ben Widawsky <[email protected]>
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f1800ca..8aafa45 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3338,6 +3338,8 @@ static void ironlake_init_clock_gating(struct drm_device
*dev)
I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0);
+ I915_WRITE(CACHE_MODE_0,
+ _MASKED_BIT_ENABLE(CM0_RC_PIPELINE_FLUSH_DISABLE));
/*
* Based on the document from hardware guys the following bits
* should be set unconditionally in order to enable FBC.
--
1.7.12.2
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