This means moving WaTempDisableDOPClkGating as well. Notice that BXT implements a similar WA to WaProgramL3SqcReg1Default but, according to the BSpec, it does not require WaTempDisableDOPClkGating.
v2: Use pre-/post- hook calls (Chris) Signed-off-by: Oscar Mateo <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Imre Deak <[email protected]> --- drivers/gpu/drm/i915/i915_drv.h | 10 ++++++ drivers/gpu/drm/i915/intel_pm.c | 46 ++----------------------- drivers/gpu/drm/i915/intel_workarounds.c | 59 ++++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f34e318..620a8f5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1968,8 +1968,18 @@ struct i915_frontbuffer_tracking { unsigned flip_bits; }; +struct i915_wa_reg; + +typedef void (* wa_hook_func)(struct drm_i915_private *dev_priv, + struct i915_wa_reg *wa); + struct i915_wa_reg { i915_reg_t addr; + + wa_hook_func pre_hook; + wa_hook_func post_hook; + u32 hook_data; + u32 value; /* bitmask representing WA bits */ u32 mask; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f1e3a04..0fc0670 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8391,39 +8391,10 @@ static void lpt_suspend_hw(struct drm_i915_private *dev_priv) } } -static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, - int general_prio_credits, - int high_prio_credits) -{ - u32 misccpctl; - u32 val; - - /* WaTempDisableDOPClkGating:bdw */ - misccpctl = I915_READ(GEN7_MISCCPCTL); - I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); - - val = I915_READ(GEN8_L3SQCREG1); - val &= ~L3_PRIO_CREDITS_MASK; - val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits); - val |= L3_HIGH_PRIO_CREDITS(high_prio_credits); - I915_WRITE(GEN8_L3SQCREG1, val); - - /* - * Wait at least 100 clocks before re-enabling clock gating. - * See the definition of L3SQCREG1 in BSpec. - */ - POSTING_READ(GEN8_L3SQCREG1); - udelay(1); - I915_WRITE(GEN7_MISCCPCTL, misccpctl); -} - static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) { ilk_init_lp_watermarks(dev_priv); - /* WaProgramL3SqcReg1Default:bdw */ - gen8_set_l3sqc_credits(dev_priv, 30, 2); - lpt_init_clock_gating(dev_priv); } @@ -8658,16 +8629,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); } -static void chv_init_clock_gating(struct drm_i915_private *dev_priv) -{ - /* - * WaProgramL3SqcReg1Default:chv - * See gfxspecs/Related Documents/Performance Guide/ - * LSQC Setting Recommendations. - */ - gen8_set_l3sqc_credits(dev_priv, 38, 2); -} - static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) { uint32_t dspclk_gate; @@ -8795,13 +8756,12 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || - IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_BROXTON(dev_priv) || IS_SKYLAKE(dev_priv)) + IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv) || + IS_BROXTON(dev_priv) || IS_SKYLAKE(dev_priv) || + IS_CHERRYVIEW(dev_priv)) dev_priv->display.init_clock_gating = nop_init_clock_gating; else if (IS_BROADWELL(dev_priv)) dev_priv->display.init_clock_gating = bdw_init_clock_gating; - else if (IS_CHERRYVIEW(dev_priv)) - dev_priv->display.init_clock_gating = chv_init_clock_gating; else if (IS_HASWELL(dev_priv)) dev_priv->display.init_clock_gating = hsw_init_clock_gating; else if (IS_IVYBRIDGE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 0a88c92..04f6af9 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -521,7 +521,14 @@ static void mmio_workarounds_apply(struct drm_i915_private *dev_priv, for (i = 0; i < count; i++) { u32 value = I915_READ(wa[i].addr); + + if (wa[i].pre_hook) + wa[i].pre_hook(dev_priv, &wa[i]); + I915_WRITE(wa[i].addr, (value & ~wa[i].mask) | wa[i].value); + + if (wa[i].post_hook) + wa[i].post_hook(dev_priv, &wa[i]); } } @@ -561,8 +568,35 @@ static int gt_wa_add(struct drm_i915_private *dev_priv, #define GT_WA_SET_FIELD(addr, mask, value) \ GT_WA_REG(addr, (mask), (value)) +/* WaTempDisableDOPClkGating */ +static void disable_dop_clock_gating(struct drm_i915_private *dev_priv, + struct i915_wa_reg *wa) +{ + u32 misccpctl = I915_READ(GEN7_MISCCPCTL); + + wa->hook_data = misccpctl; + I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); +} + +/* WaTempDisableDOPClkGating */ +static void enable_dop_clock_gating(struct drm_i915_private *dev_priv, + struct i915_wa_reg *wa) +{ + u32 misccpctl = wa->hook_data; + + /* + * Wait at least 100 clocks before re-enabling clock + * gating. See the definition of L3SQCREG1 in BSpec. + */ + POSTING_READ(GEN8_L3SQCREG1); + udelay(1); + I915_WRITE(GEN7_MISCCPCTL, misccpctl); +} + static int bdw_gt_workarounds_init_early(struct drm_i915_private *dev_priv) { + u32 idx; + /* The GTT cache must be disabled if the system is using 2M pages. */ bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_2M); @@ -585,11 +619,24 @@ static int bdw_gt_workarounds_init_early(struct drm_i915_private *dev_priv) GT_WA_SET_FIELD(HSW_GTT_CACHE_EN, 0xFFFFFFFF, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); + /* + * WaProgramL3SqcReg1Default:bdw + * See "gfxspecs/Related Documents/Performance Guide/LSQC Setting + * Recommendations" and also WaTempDisableDOPClkGating. + */ + GT_WA_SET_FIELD(GEN8_L3SQCREG1, L3_PRIO_CREDITS_MASK, + L3_GENERAL_PRIO_CREDITS(30) | L3_HIGH_PRIO_CREDITS(2)); + idx = dev_priv->workarounds.gt_wa_count - 1; + dev_priv->workarounds.gt_wa_reg[idx].pre_hook = enable_dop_clock_gating; + dev_priv->workarounds.gt_wa_reg[idx].post_hook = disable_dop_clock_gating; + return 0; } static int chv_gt_workarounds_init_early(struct drm_i915_private *dev_priv) { + u32 idx; + /* WaVSRefCountFullforceMissDisable:chv */ /* WaDSRefCountFullforceMissDisable:chv */ GT_WA_CLR_BIT(GEN7_FF_THREAD_MODE, GEN8_FF_DS_REF_CNT_FFME | @@ -611,6 +658,17 @@ static int chv_gt_workarounds_init_early(struct drm_i915_private *dev_priv) /* WaDisableSDEUnitClockGating:chv */ GT_WA_SET_BIT(GEN8_UCGCTL6, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + /* + * WaProgramL3SqcReg1Default:chv + * See "gfxspecs/Related Documents/Performance Guide/LSQC Setting + * Recommendations" and also WaTempDisableDOPClkGating. + */ + GT_WA_SET_FIELD(GEN8_L3SQCREG1, L3_PRIO_CREDITS_MASK, + L3_GENERAL_PRIO_CREDITS(38) | L3_HIGH_PRIO_CREDITS(2)); + idx = dev_priv->workarounds.gt_wa_count - 1; + dev_priv->workarounds.gt_wa_reg[idx].pre_hook = enable_dop_clock_gating; + dev_priv->workarounds.gt_wa_reg[idx].post_hook = disable_dop_clock_gating; + return 0; } @@ -699,6 +757,7 @@ static int bxt_gt_workarounds_init_early(struct drm_i915_private *dev_priv) } /* WaProgramL3SqcReg1DefaultForPerf:bxt */ + /* Does not require WaTempDisableDOPClkGating anymore */ if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) GT_WA_SET_FIELD(GEN8_L3SQCREG1, L3_PRIO_CREDITS_MASK, L3_GENERAL_PRIO_CREDITS(62) | -- 1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
