On Wed, Oct 4, 2017 at 3:54 PM, Runyan, Arthur J <[email protected]> wrote: > I think the failure was with one particularly slow eDP panel, but it is safer > to apply this to all ports. >
Thanks Art. Anyone else have thoughts/comments on this, or should this be good for merge now? Thanks! -James > -----Original Message----- > From: Vivi, Rodrigo > Sent: Wednesday, 4 October, 2017 1:25 PM > To: Ausmus, James <[email protected]> > Cc: [email protected]; [email protected]; > [email protected]; Runyan, Arthur J <[email protected]>; > [email protected] > Subject: Re: [PATCH v2 2/2] drm/i915/bdw: Fix DP_AUX_CH_CTL_TIME_OUT setting > > On Wed, Oct 04, 2017 at 08:09:22PM +0000, James Ausmus wrote: >> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A. >> Set BDW to 600us unconditionally. > > Besides that statement I also found on BSpec: > > " > Workaround > Project > BDW, EXCLUDE(CHV) > Set the Timeout timer value to at least 600us before initiating a transaction. > " > > Also I tracked this on the log and arrived to commit 'a81a507d487c > ("drm/i915/bdw: Change dp aux timeout to 600us on DDIA")' > > It seems during BDW enabling HW team found that need but only for port A > and later they might have extended it and we never noticed. > > Ccin't Art and Ben here to see if they can comment on that. > > But I believe we should add this so > > Reviewed-by: Rodrigo Vivi <[email protected]> > >> >> v2: >> -Split in to two patches (Rodrigo) >> >> Cc: Jani Nikula <[email protected]> >> Cc: Ville Syrjälä <[email protected]> >> Signed-off-by: James Ausmus <[email protected]> >> --- >> drivers/gpu/drm/i915/intel_dp.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c >> b/drivers/gpu/drm/i915/intel_dp.c >> index 5b4c9484575b..df301e00d9d9 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -1019,7 +1019,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp >> *intel_dp, >> else >> precharge = 5; >> >> - if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A) >> + if (IS_BROADWELL(dev_priv)) >> timeout = DP_AUX_CH_CTL_TIME_OUT_600us; >> else >> timeout = DP_AUX_CH_CTL_TIME_OUT_400us; >> -- >> 2.14.1 >> -- James Ausmus _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
