On 4 October 2017 at 13:43, Lionel Landwerlin <[email protected]> wrote: > On 04/10/17 12:46, Matthew Auld wrote: >> >> On 4 October 2017 at 12:19, Lionel Landwerlin >> <[email protected]> wrote: >>> >>> From: Robert Bragg <[email protected]> >>> >>> Signed-off-by: Robert Bragg <[email protected]> >>> Signed-off-by: Lionel Landwerlin <[email protected]>
<SNIP> >>> + bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", >>> 4096, 64); >> >> alignment=64 ? > > > Alignment requirement for MI_RPC are lower than with surfaces and indeed > 64bytes. The minimum gtt alignment is 4K, so specifying 64bytes doesn't make sense. _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
