Check that all the power well IDs are unique on the given platform.
Signed-off-by: Imre Deak <[email protected]>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 27c69f9..f0bdb63 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2563,6 +2563,8 @@ static uint32_t get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ u64 power_well_ids;
+ int i;
i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
i915.disable_power_well);
@@ -2599,6 +2601,15 @@ int intel_power_domains_init(struct drm_i915_private
*dev_priv)
set_power_wells(power_domains, i9xx_always_on_power_well);
}
+ power_well_ids = 0;
+ for (i = 0; i < power_domains->power_well_count; i++) {
+ enum i915_power_well_id id = power_domains->power_wells[i].id;
+
+ WARN_ON(id >= sizeof(power_well_ids) * 8);
+ WARN_ON(power_well_ids & BIT(id));
+ power_well_ids |= BIT(id);
+ }
+
return 0;
}
--
2.7.4
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