On Thu, Jun 22, 2017 at 12:25:24PM -0700, Manasi Navare wrote: > Now the VBT.seq->t11_t12 value adds 100ms to both Gen9_LP > as well as non Gen9_LP cases so no need to special case > and do -1 during HW readout and +1 during pp_div write > for Gen9_LP/CNP case. > > Signed-off-by: Manasi Navare <[email protected]> > Suggested-by: Ville Syrjala <[email protected]> > Cc: Ville Syrjala <[email protected]> > Cc: Clint Taylor <[email protected]>
lgtm Reviewed-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_dp.c | 10 +++------- > 1 file changed, 3 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index be9e17a..67bc8a7a 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -5178,12 +5178,8 @@ intel_pps_readout_hw_state(struct drm_i915_private > *dev_priv, > PANEL_POWER_DOWN_DELAY_SHIFT; > > if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { > - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > - BXT_POWER_CYCLE_DELAY_SHIFT; > - if (tmp > 0) > - seq->t11_t12 = (tmp - 1) * 1000; > - else > - seq->t11_t12 = 0; > + seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > + BXT_POWER_CYCLE_DELAY_SHIFT) * 1000; > } else { > seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; > @@ -5342,7 +5338,7 @@ intel_dp_init_panel_power_sequencer_registers(struct > drm_device *dev, > if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { > pp_div = I915_READ(regs.pp_ctrl); > pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; > - pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) > + pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) > << BXT_POWER_CYCLE_DELAY_SHIFT); > } else { > pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; > -- > 2.1.4 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
