Cc: Dmitry Rogozhkin <[email protected]>
Cc: Chris Wilson <[email protected]>
Signed-off-by: Oscar Mateo <[email protected]>
---
tests/pm_sseu.c | 105 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/tests/pm_sseu.c b/tests/pm_sseu.c
index 7d4b33c..1fb36c5 100644
--- a/tests/pm_sseu.c
+++ b/tests/pm_sseu.c
@@ -352,6 +352,108 @@ full_enable(void)
check_full_enable(&stat);
}
+#define GEN8_R_PWR_CLK_STATE (0x20C8)
+#define GEN8_RPCS_ENABLE (1 << 31)
+
+#define MI_STORE_REGISTER_MEM_64_BIT_ADDR ((0x24 << 23) | 2)
+
+static uint32_t read_pwrclk_state(drm_intel_bufmgr *bufmgr,
+ struct intel_batchbuffer *batch,
+ drm_intel_context *context)
+{
+ uint32_t rpcs_config;
+ uint32_t *data;
+ drm_intel_bo *dst_bo;
+
+ dst_bo = drm_intel_bo_alloc(bufmgr, "dst", 4, 4096);
+
+ BEGIN_BATCH(3, 1);
+ OUT_BATCH(MI_STORE_REGISTER_MEM_64_BIT_ADDR);
+ OUT_BATCH(GEN8_R_PWR_CLK_STATE);
+ OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ ADVANCE_BATCH();
+
+ intel_batchbuffer_flush_with_context(batch, context);
+
+ drm_intel_bo_map(dst_bo, 1);
+
+ data = dst_bo->virtual;
+ rpcs_config = *data;
+
+ drm_intel_bo_unmap(dst_bo);
+
+ drm_intel_bo_unreference(dst_bo);
+
+ return rpcs_config;
+}
+
+#define LOCAL_MI_LOAD_REGISTER_IMM (0x22 << 23)
+
+#define GFX_OP_PIPE_CONTROL(len)
((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
+#define PIPE_CONTROL_CS_STALL (1<<20)
+#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12)
+#define PIPE_CONTROL_FLUSH_ENABLE (1<<7)
+#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
+
+static void write_pwrclk_state(drm_intel_bufmgr *bufmgr,
+ struct intel_batchbuffer *batch,
+ drm_intel_context *context,
+ uint32_t rpcs_config)
+{
+ drm_intel_bo *dst_bo;
+
+ dst_bo = drm_intel_bo_alloc(bufmgr, "scratch", 4, 4096);
+
+ BEGIN_BATCH(9, 1);
+ OUT_BATCH(LOCAL_MI_LOAD_REGISTER_IMM | 1);
+ OUT_BATCH(GEN8_R_PWR_CLK_STATE);
+ OUT_BATCH(rpcs_config);
+ OUT_BATCH(GFX_OP_PIPE_CONTROL(6));
+ OUT_BATCH(PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_DC_FLUSH_ENABLE |
+ PIPE_CONTROL_FLUSH_ENABLE |
+ PIPE_CONTROL_CS_STALL);
+ OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
+ intel_batchbuffer_flush_with_context(batch, context);
+
+ drm_intel_bo_unreference(dst_bo);
+}
+
+/* Makes sure userspace can configure GEN8_R_PWR_CLK_STATE (e.g. is
whitelisted) */
+static void
+pwrclk_state(void)
+{
+ drm_intel_context *context;
+ uint32_t rpcs_config;
+ bool rpcs_enabled;
+
+ /*
+ * Gen8 BDW is the first case in which usermode can configure their
+ * own render power gating
+ */
+ igt_require(gem.gen >= 8);
+
+ context = drm_intel_gem_context_create(gem.bufmgr);
+
+ rpcs_config = read_pwrclk_state(gem.bufmgr, gem.batch, context);
+ rpcs_enabled = rpcs_config & GEN8_RPCS_ENABLE;
+
+ rpcs_config ^= GEN8_RPCS_ENABLE;
+ write_pwrclk_state(gem.bufmgr, gem.batch, context, rpcs_config);
+
+ rpcs_config = read_pwrclk_state(gem.bufmgr, gem.batch, context);
+ igt_assert_neq(rpcs_enabled, !!(rpcs_config & GEN8_RPCS_ENABLE));
+
+ drm_intel_gem_context_destroy(context);
+}
+
static void
exit_handler(int sig)
{
@@ -370,4 +472,7 @@ igt_main
igt_subtest("full-enable")
full_enable();
+
+ igt_subtest("pwrclk-state")
+ pwrclk_state();
}
--
1.9.1
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