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On ti, 2017-04-04 at 23:11 +0100, Matthew Auld wrote:
> v2:
> - move out pde/pdpe bit definitions until later
> - tidyup the page size definitions, use BIT
> - introduce helper for detecting invalid page sizes
>
> Signed-off-by: Matthew Auld <[email protected]>
> Cc: Mika Kuoppala <[email protected]>
> Cc: Chris Wilson <[email protected]>
<SNIP>
> @@ -2876,6 +2877,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
> #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
> #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
> +#define SUPPORTS_PAGE_SIZE(dev_priv, page_size) \
> + ((dev_priv)->info.page_size_mask & (page_size))
Why not HAS_PAGE_SIZE()?
> +#define is_valid_gtt_page_size(page_size) \
> + (is_power_of_2(page_size) && \
> + (page_size) & I915_GTT_PAGE_SIZE_MASK)
When would this matter? I'd assume we always gotta rely on device info.
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -56,6 +56,10 @@
> .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
>
> /* Keep in gen based order, and chronological order within a gen */
> +
> +#define GEN_DEFAULT_PAGE_SZ \
> + .page_size_mask = I915_GTT_PAGE_SIZE_4K
GEN_DEFAULT_PAGE_SIZES
> @@ -346,13 +358,18 @@ static const struct intel_device_info
> intel_cherryview_info = {
> .has_aliasing_ppgtt = 1,
> .has_full_ppgtt = 1,
> .display_mmio_offset = VLV_DISPLAY_BASE,
> + .page_size_mask = I915_GTT_PAGE_SIZE_4K | I915_GTT_PAGE_SIZE_64K |
> I915_GTT_PAGE_SIZE_2M | I915_GTT_PAGE_SIZE_1G,
Split long line.
> GEN_CHV_PIPEOFFSETS,
> CURSOR_OFFSETS,
> > CHV_COLORS,
> };
>
> +#define GEN9_DEFAULT_PAGE_SZ \
> + .page_size_mask = I915_GTT_PAGE_SIZE_4K | I915_GTT_PAGE_SIZE_64K |
> I915_GTT_PAGE_SIZE_2M | I915_GTT_PAGE_SIZE_1G
GEN9_DEFAULT_PAGE_SIZES, also split long line.
With above,
Reviewed-by: Joonas Lahtinen <[email protected]>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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