On Fri, Nov 25, 2016 at 12:57:01PM +0200, Imre Deak wrote: > commit 848496e5902833600f7992f4faa82dc1546051ba > Author: Ville Syrjälä <[email protected]> > Date: Wed Jul 13 16:32:03 2016 +0300 > > drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on > SKL > > increased the timeout to match the spec, but we still see a timeout on > at least one SKL. A CDCLK change request following the failed one will > succeed nevertheless, so let's try to increase the timeout to 10ms. > > v2: > - Use 1ms poll period instead of 10us. (Chris) > > Cc: Ville Syrjälä <[email protected]> > Cc: Chris Wilson <[email protected]> > Reference: https://bugs.freedesktop.org/show_bug.cgi?id=97929 > Signed-off-by: Imre Deak <[email protected]>
If you are happy with it, so am I! Reviewed-by: Chris Wilson <[email protected]> Possibly time to volunteer someone to look at the poll interval again. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
