On Wed, 05 Oct 2011 11:07:53 -0700 Keith Packard <[email protected]> wrote:
> On Wed, 5 Oct 2011 10:25:18 -0700, Jesse Barnes <[email protected]> > wrote: > > > Add a macro for accessing the two pipe PLLs and add a check to make sure > > we don't access a non-existent one in the enable/disable functions. > > So, I haven't read through the specs, but are the PLLs tied to specific > pipes? Or are we really talking about a different object here, and just > mis-naming it as a 'pipe'? They're not hardwired; we can use the DPLL_SEL reg to control which PLL drives which transcoder. Unfortunately our old pipe terminology is a bit outdated with the PCH split. It used to be the pipe was fairly self-contained: a PLL with pipe and plane controls. Now it's split across the CPU and PCH with FDI in between (sometimes) and transcoder configuration (sometimes with DP). -- Jesse Barnes, Intel Open Source Technology Center
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