On Wed, 10 Nov 2010 07:54:12 +0000 Chris Wilson <[email protected]> wrote:
> On Wed, 10 Nov 2010 08:36:20 +0800, "Zou, Nanhai" > <[email protected]> wrote: > > >>-----Original Message----- > > >>From: Chris Wilson [mailto:[email protected]] > > >>Sent: 2010年11月9日 18:50 > > >>To: Zou, Nanhai; [email protected]; Zhao, Jian J > > >>Subject: RE: [PATCH] drm/i915/ringbuffer: set force wake bit > > >>before reading ring register > > >> > > >>On Tue, 9 Nov 2010 17:17:07 +0800, "Zou, Nanhai" > > >><[email protected]> wrote: > > >> > > >>> I have tested this patch with the read ring head from status > > >>> page workaround > > >>patch reverted. > > >>> Seems it works on my SNB box. > > >> > > >>I needed to add a udelay(100) to i915_safe_read for my rev 8. Can > > >>you check if there is a recommended delay for FORCEWAKE? > > >>-Chris > > >> > > Dose a post read to FORCEWAKE help? > > No, tried a POSTING_READ(FORCEWAKE) first and it wasn't until I added > the udelay() between the READ(FORCEWAKE) and the READ(reg) that it > returned the correct results in a single call. I think these regs will be affected by the ucode on the GPU; we may need specific delays after some operations. Have you tried asking the hw guys what the best practices are here? -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
