On Wed, 13 Oct 2010 16:40:11 +0800 Zhenyu Wang <[email protected]> wrote:
> FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to Sandybridge. > > Signed-off-by: Zhenyu Wang <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 5 ++++- > 1 files changed, 4 insertions(+), 1 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 8e98d70..b711e98 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3709,7 +3709,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, > * Hence the bw of each lane in terms of the mode signal > * is: > */ > - link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; > + if (IS_GEN5(dev)) > + link_bw = intel_fdi_link_freq(dev) * > MHz(100)/KHz(1)/10; > + else > + link_bw = 270000; > } > > /* determine panel color depth */ So this gets the display working again with current bits? -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
