On Mon, 2010-04-26 at 22:19 +0100, Peter Clifton wrote: > @@ -3439,11 +3442,16 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) > > /* use legacy palette for Ironlake */ > if (IS_IRONLAKE(dev)) > - palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : > - LGC_PALETTE_B; > + pal_reg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : > + LGC_PALETTE_B; > + > + /* Switch to 8-bit gamma mode */ > + pipeconf &= ~PIPEACONF_GAMMA; > + I915_WRITE(pipeconf_reg, pipeconf); > + I915_READ(pipeconf_reg);
This is wrong for gen5, where bits 25 and 24 control gamma: Value Name Description Project 00b 8 bit 8-bit Legacy Palette Mode All 01b 10 bt 10-bit Precision Palette Mode All 10b 12 bit 12-bit Interpolated Gamma Mode All 11b Reserved Reserved All Where 10-bit is a real 1024-stop gamma, and 12-bit is 512 lerp'd stops (like gen4's 129 lerp'd stops). I don't think it'd matter in the real world since I doubt any OEM is insane enough to set up 12-bit in the BIOS, but. On gen4 and earlier though, bit 25 is border color enable. Pretty sure we only use that in VGA load detection. Although, we use it in VGA load detection even on gen5, which means load detection on gen5 almost certainly does not work. Patch looks good otherwise. - ajax
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