The P30 is pritty nice. I use 2x8 Pins for RX_I und RX_Q to foward it to an
external FPGA
If anyboy is intressed sent me a mail ;)
process(host_clk_i)
begin
if rising_edge(host_clk_i) then -- vll falling_edge
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
rx_i <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
LET_Q <= adc_data_i xor rx_q_invert_mask;
LET_I <= rx_i;
end if;
end if;
end process;
_______________________________________________
HackRF-dev mailing list
[email protected]
https://pairlist9.pair.net/mailman/listinfo/hackrf-dev
