Paul Hartman schrieb: > On Thu, Jun 11, 2009 at 3:07 PM, Kelly Hirai<ke...@met.fsu.edu> wrote: >> the N270 is a single core with hyperthreading, which will apear as 2 >> cpus (with the same core id) in dmesg. > > Ah, I forgot about hyperthreading masquerading as multiple CPUs. In > that case, Maxim can safely disable SMP if he wants to. I don't know > if the theoretical speed gains of disabling SMP outweigh the > theoretical speed gains of enabling hyperthreading. I think it'll > probably be about the same either way. >
Well, I don't know about real workloads but once I did a little benchmark: One versus two instances of `dd < /dev/zero | md5sum`. Two instances had a 30% higher throughput than one. I haven't tried it with disabled SMP but I really can't imagine that the extra scheduling would cost nearly enough to compensate for this. From a technical point of view, I think HT makes more sense for an Atom than for a Nehalem: The Atom has only one pipeline, no out-of-order execution and probably a less effective branch prediction. HT might compensate this. However, I'm wondering if it wouldn't have been better to implement out-of-order execution instead of HT (like VIA Nano, for example). Maybe HT doesn't need as many transistors as out-of-order execution? In the end, unless there is some hard evidence against the use of HT, I'd say: They've spend their transistor budget on HT, now we should use what we've got.
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