On Jul 28, 2012 8:03 AM, "Michael Mol" <mike...@gmail.com> wrote: > > On Fri, Jul 27, 2012 at 8:30 PM, microcai <micro...@fedoraproject.org> wrote:
--- >8 Major Snippage > > As far as I can tell, AMD chip suffered with a lot of I/O. Their > > Hyper-transport seems not competitive with Intel's ring bus > Wasn't Intel's answer to HyperTransport is the QuickPath bus? IIRC, the ring bus is internal to a processor. (I could be wrong, though). > (please don't top-post, especially if the thread's already been > primarily organized as bottom-post) > > I hadn't read that, but remember that HyperTransport is intended for a > mesh architecture. In single-CPU systems, you'll only have one HT > link, the link between your CPU and your north bridge. In multi-CPU > systems, you'll have additional links between the CPUs. In systems > with many CPUs, you may even have a fully-connected mesh. > > The I/O characteristics will greatly depend on the topology of your network. > > That said, HyperTransport may just be getting old; when it came out, > it (and AMD's crossbar switch for memory management) beat the pants > off of Intel's SMP solution. Intel's solution ran at lower and lower > clock rates the more CPUs you added, and their first pass at multicore > gave each core its own port onto the memory bus, with predictably poor > results. Intel's had plenty of time to catch up, but with their > price-per-part, it's taken me a long time to pay much attention. > Again, I might be mistaken, but IIRC HyperTransport's throughput depends on how many channels are provided, so there's no theoretical limitation to its throughput, just practical considerations. (E.g., tracing issues). > (It also doesn't help that Jon "Hannibal" Stokes stopped writing > detailed technical articles for Ars Technica; I sincerely miss him and > the precision and clarity of his writing on such arcane subjects.) > That makes the two of us bro... BTW, my handle there's "pepoluan", just in case you see it in the forums. Rgds,
