[gentoo-commits] repo/gentoo:master commit in: eclass/

[Michał Górny]

commit:     9f52acdde8440a1ebc0ddd5145054d2b44afe690
Author:     Michał Górny <mgorny <AT> gentoo <DOT> org>
AuthorDate: Tue Dec 27 18:44:41 2022 +0000
Commit:     Michał Górny <mgorny <AT> gentoo <DOT> org>
CommitDate: Tue Dec 27 18:45:25 2022 +0000
URL:        https://gitweb.gentoo.org/repo/gentoo.git/commit/?id=9f52acdd

llvm.org.eclass: Add experimental Xtensa target to 16.x

Signed-off-by: Michał Górny <mgorny <AT> gentoo.org>

 eclass/llvm.org.eclass | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/eclass/llvm.org.eclass b/eclass/llvm.org.eclass
index c118298595a8..92c474433b07 100644
--- a/eclass/llvm.org.eclass
+++ b/eclass/llvm.org.eclass
@@ -194,7 +194,7 @@ case ${LLVM_MAJOR} in
                        PowerPC RISCV Sparc SystemZ VE WebAssembly X86 XCore
                )
                ;;
-       *)
+       15)
                ALL_LLVM_EXPERIMENTAL_TARGETS=(
                        ARC CSKY DirectX LoongArch M68k SPIRV
                )
@@ -203,6 +203,15 @@ case ${LLVM_MAJOR} in
                        PowerPC RISCV Sparc SystemZ VE WebAssembly X86 XCore
                )
                ;;
+       *)
+               ALL_LLVM_EXPERIMENTAL_TARGETS=(
+                       ARC CSKY DirectX LoongArch M68k SPIRV Xtensa
+               )
+               ALL_LLVM_PRODUCTION_TARGETS=(
+                       AArch64 AMDGPU ARM AVR BPF Hexagon Lanai Mips MSP430 
NVPTX
+                       PowerPC RISCV Sparc SystemZ VE WebAssembly X86 XCore
+               )
+               ;;
 esac
 
 ALL_LLVM_TARGET_FLAGS=(