commit: 451eaa396936654d9772705c46a620bcd202fe6b Author: Michał Górny <mgorny <AT> gentoo <DOT> org> AuthorDate: Tue Oct 1 12:11:11 2019 +0000 Commit: Michał Górny <mgorny <AT> gentoo <DOT> org> CommitDate: Tue Oct 1 12:22:27 2019 +0000 URL: https://gitweb.gentoo.org/repo/gentoo.git/commit/?id=451eaa39
profiles/desc/llvm_targets.desc: RISCV & WASM are no longer exp Signed-off-by: Michał Górny <mgorny <AT> gentoo.org> profiles/desc/llvm_targets.desc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/profiles/desc/llvm_targets.desc b/profiles/desc/llvm_targets.desc index e83d886dedb..6a45455f4c3 100644 --- a/profiles/desc/llvm_targets.desc +++ b/profiles/desc/llvm_targets.desc @@ -12,9 +12,9 @@ Mips - MIPS CPU target (includes MIPS64) MSP430 - MSP430 CPU target (experimental) NVPTX - NVIDIA PTX (GPU) target (32-bit and 64-bit) PowerPC - PowerPC CPU target (PPC32 and PPC64) -RISCV - RISC-V CPU target [EXPERIMENTAL] +RISCV - RISC-V CPU target Sparc - Sparc CPU target SystemZ - SystemZ (s390x) CPU target -WebAssembly - WebAssembly backend [EXPERIMENTAL] +WebAssembly - WebAssembly backend X86 - X86 CPU target (includes amd64) XCore - XCore CPU target
