commit: ad10f29c19cc110e991536e338b9485cafde18eb Author: Huang Rui <vowstar <AT> gmail <DOT> com> AuthorDate: Wed Jan 14 10:17:04 2026 +0000 Commit: Rui Huang <vowstar <AT> gmail <DOT> com> CommitDate: Wed Jan 14 10:17:19 2026 +0000 URL: https://gitweb.gentoo.org/repo/proj/guru.git/commit/?id=ad10f29c
sci-electronics/yosys: add 0.61, drop 0.60 Closes: https://bugs.gentoo.org/933183 Closes: https://bugs.gentoo.org/937505 Closes: https://bugs.gentoo.org/931001 Signed-off-by: Huang Rui <vowstar <AT> gmail.com> sci-electronics/yosys/Manifest | 2 +- .../yosys/{yosys-0.60.ebuild => yosys-0.61.ebuild} | 29 +++++++++++++++++++--- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/sci-electronics/yosys/Manifest b/sci-electronics/yosys/Manifest index ef16a2a5b1..b09decf139 100644 --- a/sci-electronics/yosys/Manifest +++ b/sci-electronics/yosys/Manifest @@ -1 +1 @@ -DIST yosys-0.60.tar.gz 10765490 BLAKE2B 8c2cdde2a2891573e4c8176e38a1aa667136f82854b48730ad350bb5733ee4d3b30f347564ac4172636e427818d514083f17d84399cb41ef0151df4809d67416 SHA512 9f518f9eb28f4f92a31cd58a034df497ff8fe959ac72a756a452c3ab93b1075ef19889d65f014ae64ab4b7ef63d3d5dbc65828e2fcf81151576c3bf917ed7a08 +DIST yosys-0.61.tar.gz 10906158 BLAKE2B 63e0477252bea729c90cac4469cf5b585b6110364450d64c993fb588883e8a97e890fe55aa5ccb2f696ac26660490e3252687ac4395fa50324902881c6b8e117 SHA512 0eb5e76a260dcdf4b2cdc42b7feabd4b9331843ae3445fd33785828d1d601794bdbd4f7940acbccbc39681ced5d10ad03b545775668076b5fbab92e3acd3475e diff --git a/sci-electronics/yosys/yosys-0.60.ebuild b/sci-electronics/yosys/yosys-0.61.ebuild similarity index 56% rename from sci-electronics/yosys/yosys-0.60.ebuild rename to sci-electronics/yosys/yosys-0.61.ebuild index 6aa8136901..86e4c6483a 100644 --- a/sci-electronics/yosys/yosys-0.60.ebuild +++ b/sci-electronics/yosys/yosys-0.61.ebuild @@ -3,29 +3,52 @@ EAPI=8 +PYTHON_COMPAT=( python3_{11..14} ) + +inherit python-any-r1 + DESCRIPTION="framework for Verilog RTL synthesis" HOMEPAGE="https://yosyshq.net/yosys/"; SRC_URI=" https://github.com/YosysHQ/${PN}/releases/download/v${PV}/yosys.tar.gz -> ${P}.tar.gz " S="${WORKDIR}" + LICENSE="ISC" SLOT="0" KEYWORDS="~amd64" +IUSE="tcl" RDEPEND=" - dev-libs/boost + dev-libs/boost:= + dev-libs/libffi:= + llvm-core/clang:= media-gfx/xdot - llvm-core/clang + sys-libs/ncurses:= + sys-libs/readline:= + virtual/zlib + tcl? ( dev-lang/tcl:= ) " DEPEND="${RDEPEND}" -BDEPEND="dev-vcs/git" +BDEPEND=" + ${PYTHON_DEPS} + dev-vcs/git + virtual/pkgconfig +" src_configure() { cat <<-__EOF__ >> Makefile.conf || die PREFIX := ${EPREFIX}/usr STRIP := @echo "skipping strip" + CXXFLAGS += ${CXXFLAGS} + LINKFLAGS += ${LDFLAGS} + PYTHON_EXECUTABLE := ${PYTHON} __EOF__ + + if ! use tcl; then + echo "ENABLE_TCL := 0" >> Makefile.conf || die + fi + default }
