commit: 635270aa5e057c2179a7edc698854d621b0eeade Author: Arisu Tachibana <alicef <AT> gentoo <DOT> org> AuthorDate: Mon Oct 27 14:25:50 2025 +0000 Commit: Arisu Tachibana <alicef <AT> gentoo <DOT> org> CommitDate: Mon Oct 27 14:39:58 2025 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=635270aa
Add patch 1710 disable sse4a Signed-off-by: Arisu Tachibana <alicef <AT> gentoo.org> 0000_README | 4 ++++ 1710_disable_sse4a.patch | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/0000_README b/0000_README index f15fc4f0..6ad0c146 100644 --- a/0000_README +++ b/0000_README @@ -71,6 +71,10 @@ Patch: 1700_sparc-address-warray-bound-warnings.patch From: https://github.com/KSPP/linux/issues/109 Desc: Address -Warray-bounds warnings +Patch: 1710_disable_sse4a.patch +From: https://lore.kernel.org/all/20251027124049.GAaP9oUaUtzzHUK4j4@fat_crate.local/ +Desc: Disable SSE4A + Patch: 1730_parisc-Disable-prctl.patch From: https://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git Desc: prctl: Temporarily disable prctl(PR_SET_MDWE) on parisc diff --git a/1710_disable_sse4a.patch b/1710_disable_sse4a.patch new file mode 100644 index 00000000..55283380 --- /dev/null +++ b/1710_disable_sse4a.patch @@ -0,0 +1,38 @@ +Subject: x86: Disable SSE4A +Sent: October 27, 2025 11:40:59 AM UTC +From: Peter Zijlstra <[email protected]> +To: [email protected], Leyvi Rose <[email protected]> +Cc: Samuel Holland <[email protected]>, "Christian König" <[email protected]>, Masami Hiramatsu <[email protected]> + +Hi, + +Leyvi Rose reported that his X86_NATIVE_CPU=y build is failing because +our instruction decoder doesn't support SSE4A and the AMDGPU code seems +to be generating those with his compiler of choice (CLANG+LTO). + +Now, our normal build flags disable SSE MMX SSE2 3DNOW AVX, but then +CC_FLAGS_FPU re-enable SSE SSE2. + +Since nothing mentions SSE3 or SSE4, I'm assuming that -msse (or its +negative) control all SSE variants -- but why then explicitly enumerate +SSE2 ? + +Anyway, until the instruction decoder gets fixed, explicitly disallow +SSE4A (an AMD specific SSE4 extension). + +Fixes: ea1dcca1de12 ("x86/kbuild/64: Add the CONFIG_X86_NATIVE_CPU option to locally optimize the kernel with '-march=native'") +Signed-off-by: Peter Zijlstra (Intel) <[email protected]> +--- + +diff --git a/arch/x86/Makefile b/arch/x86/Makefile +index 4db7e4bf69f5..8fbff3106c56 100644 +--- a/arch/x86/Makefile ++++ b/arch/x86/Makefile +@@ -75,7 +75,7 @@ export BITS + # + # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53383 + # +-KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx ++KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx -mno-sse4a + KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json + KBUILD_RUSTFLAGS += -Ctarget-feature=-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2
