commit: 0dc6241a2a6ad3ab5930af0d1820c76f60ab414e
Author: Huang Rui <vowstar <AT> gmail <DOT> com>
AuthorDate: Mon May 5 03:15:41 2025 +0000
Commit: Rui Huang <vowstar <AT> gmail <DOT> com>
CommitDate: Mon May 5 03:15:41 2025 +0000
URL: https://gitweb.gentoo.org/repo/proj/guru.git/commit/?id=0dc6241a
sci-electronics/circt: enable py3.13
Signed-off-by: Huang Rui <vowstar <AT> gmail.com>
sci-electronics/circt/circt-1.37.0.ebuild | 2 +-
sci-electronics/circt/circt-1.76.0.ebuild | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/sci-electronics/circt/circt-1.37.0.ebuild
b/sci-electronics/circt/circt-1.37.0.ebuild
index 0b1a877e5..e3254ff3c 100644
--- a/sci-electronics/circt/circt-1.37.0.ebuild
+++ b/sci-electronics/circt/circt-1.37.0.ebuild
@@ -6,7 +6,7 @@ EAPI="8"
MY_PV="${PV//./\/}"
MY_LLVM_PV="d978730d8e2c10c76867b83bec2f1143d895ee7d"
CMAKE_BUILD_TYPE="Release"
-PYTHON_COMPAT=( python3_{11..12} )
+PYTHON_COMPAT=( python3_{11..13} )
inherit cmake python-r1
DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
diff --git a/sci-electronics/circt/circt-1.76.0.ebuild
b/sci-electronics/circt/circt-1.76.0.ebuild
index 55b05c8d1..ad2727dc8 100644
--- a/sci-electronics/circt/circt-1.76.0.ebuild
+++ b/sci-electronics/circt/circt-1.76.0.ebuild
@@ -6,7 +6,7 @@ EAPI="8"
MY_PV="${PV//./\/}"
MY_LLVM_PV="6595e7fa1b5588f860aa057aac47c43623169584"
CMAKE_BUILD_TYPE="Release"
-PYTHON_COMPAT=( python3_{11..12} )
+PYTHON_COMPAT=( python3_{11..13} )
inherit cmake python-r1
DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
