[gentoo-commits] repo/gentoo:master commit in: eclass/

[Michał Górny]

commit:     c44b01389c8cd7af719b5e0b7838e8315f1648e9
Author:     Michał Górny <mgorny <AT> gentoo <DOT> org>
AuthorDate: Wed Jan 22 16:32:27 2025 +0000
Commit:     Michał Górny <mgorny <AT> gentoo <DOT> org>
CommitDate: Wed Jan 22 19:15:17 2025 +0000
URL:        https://gitweb.gentoo.org/repo/gentoo.git/commit/?id=c44b0138

llvm.org.eclass: SPIRV is production since 20.0.0_pre20250122

Signed-off-by: Michał Górny <mgorny <AT> gentoo.org>

 eclass/llvm.org.eclass | 28 ++++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/eclass/llvm.org.eclass b/eclass/llvm.org.eclass
index 7d7774cfb027..414a9ef59523 100644
--- a/eclass/llvm.org.eclass
+++ b/eclass/llvm.org.eclass
@@ -185,14 +185,26 @@ case ${LLVM_MAJOR} in
                )
                ;;
        *)
-               ALL_LLVM_EXPERIMENTAL_TARGETS=(
-                       ARC CSKY DirectX M68k SPIRV Xtensa
-               )
-               ALL_LLVM_PRODUCTION_TARGETS=(
-                       AArch64 AMDGPU ARM AVR BPF Hexagon Lanai LoongArch Mips
-                       MSP430 NVPTX PowerPC RISCV Sparc SystemZ VE WebAssembly 
X86
-                       XCore
-               )
+               # TODO: limit to < 20 when we remove old snapshots
+               if ver_test ${PV} -lt 20.0.0_pre20250122; then
+                       ALL_LLVM_EXPERIMENTAL_TARGETS=(
+                               ARC CSKY DirectX M68k SPIRV Xtensa
+                       )
+                       ALL_LLVM_PRODUCTION_TARGETS=(
+                               AArch64 AMDGPU ARM AVR BPF Hexagon Lanai 
LoongArch Mips
+                               MSP430 NVPTX PowerPC RISCV Sparc SystemZ VE 
WebAssembly X86
+                               XCore
+                       )
+               else
+                       ALL_LLVM_EXPERIMENTAL_TARGETS=(
+                               ARC CSKY DirectX M68k Xtensa
+                       )
+                       ALL_LLVM_PRODUCTION_TARGETS=(
+                               AArch64 AMDGPU ARM AVR BPF Hexagon Lanai 
LoongArch Mips
+                               MSP430 NVPTX PowerPC RISCV Sparc SPIRV SystemZ 
VE
+                               WebAssembly X86 XCore
+                       )
+               fi
                ;;
 esac