Hi gem5,
i was trying to figure out the reason behind this panic
caused by simulation of 4 core using PARSEC benchmarks (prefetcher turned on
) system.switch_cpus0.break_event: break event panic triggered , panic: Halt
not implemented!
@ cycle 2297453665500
[halt:build/ALPHA_FS/cpu/o3/cpu.hh, line 386]
Any idea how to solve it?
--
*thanks®ards
*
*BISWABANDAN PANDA*
*M.S.(RESEARCH SCHOLAR)*
*RISE LAB*
*IIT MADRAS*
http://www.cse.iitm.ac.in/~biswa/
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users