On Mar 26, 2011, at 3:36 PM, Adwait Jog wrote: > Hi All: > > When one switch to detailed mode (O3) from AtomicCPU, why memory model is > still atomic ? Isn't the memory model should be timing when CPU is switched > to O3? Please note, while switching I am using either (-F option and then > m5switchcpu in .rcS script in FS mode) or make a checkpoint just before ROI > starts? > > Adwait > > def setCPUClass(options): > > atomic = False > if options.timing: > class TmpClass(TimingSimpleCPU): pass > elif options.detailed: > if not options.caches: > print "O3 CPU must be used with caches" > sys.exit(1) > class TmpClass(DerivO3CPU): pass > elif options.inorder: > if not options.caches: > print "InOrder CPU must be used with caches" > sys.exit(1) > class TmpClass(InOrderCPU): pass > else: > class TmpClass(AtomicSimpleCPU): pass > atomic = True > > CPUClass = None > test_mem_mode = 'atomic' > > if not atomic: > if options.checkpoint_restore != None or options.fast_forward: > CPUClass = TmpClass > class TmpClass(AtomicSimpleCPU): pass > else: > test_mem_mode = 'timing' > > return (TmpClass, test_mem_mode, CPUClass) > This function only set the initial mode, which is almost always atomic. When you restore from a checkpoint, you restore into an atomic cpu, execute for a couple of cycles and then switch to a timing/o3 cpu and change the memory mode when that happens.
Ali
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