diff -r 77aa0f94e7f2 -r a62ea692b826 configs/common/Simulation.py
--- a/configs/common/Simulation.py Tue Mar 08 21:43:11 2011 -0800
+++ b/configs/common/Simulation.py Fri Mar 11 15:04:32 2011 -0500
@@ -123,6 +123,11 @@
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
if options.standard_switch:
+ if not options.caches:
+ # O3 CPU must have a cache to work.
+ print "O3 CPU must be used with caches"
+ sys.exit(1)
+
switch_cpus = [TimingSimpleCPU(defer_registration=True,
cpu_id=(np+i))
for i in xrange(np)]
switch_cpus_1 = [DerivO3CPU(defer_registration=True,
cpu_id=(2*np+i))
@@ -161,15 +166,10 @@
if options.max_inst:
switch_cpus_1[i].max_insts_any_thread = options.max_inst
- if not options.caches:
- # O3 CPU must have a cache to work.
- print "O3 CPU must be used with caches"
- sys.exit(1)
-
- testsys.switch_cpus = switch_cpus
- testsys.switch_cpus_1 = switch_cpus_1
- switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i
in xrange(np)]
- switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for
i in xrange(np)]
+ testsys.switch_cpus = switch_cpus
+ testsys.switch_cpus_1 = switch_cpus_1
+ switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
+ switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in
xrange(np)]
# set the checkpoint in the cpu before m5.instantiate is called
if options.take_checkpoints != None and \
On 03/24/2011 05:04 AM, Tripti Warrier wrote:
Hi Tony,
I downloaded the latest version of m5 from the repository tried the same. It
still gives me the
same error. From where can I get the patch.
thanks and regards
Tripti
On Wed, Mar 23, 2011 at 9:30 PM, <[email protected]
<mailto:[email protected]>> wrote:
Send m5-users mailing list submissions to
[email protected] <mailto:[email protected]>
To subscribe or unsubscribe via the World Wide Web, visit
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
or, via email, send a message with subject or body 'help' to
[email protected] <mailto:[email protected]>
You can reach the person managing the list at
[email protected] <mailto:[email protected]>
When replying, please edit your Subject line so it is more specific
than "Re: Contents of m5-users digest..."
Today's Topics:
1. SE mode with switch_cpu and multiple cpus. (Tripti Warrier)
2. Re: SE mode with switch_cpu and multiple cpus. (Anthony
Gutierrez)
3. question about the DRAM model in M5 (sheng qiu)
----------------------------------------------------------------------
Message: 1
Date: Wed, 23 Mar 2011 14:39:55 +0530
From: Tripti Warrier <[email protected] <mailto:[email protected]>>
To: [email protected] <mailto:[email protected]>
Subject: [m5-users] SE mode with switch_cpu and multiple cpus.
Message-ID:
<[email protected]
<mailto:[email protected]>>
Content-Type: text/plain; charset="iso-8859-1"
Hello All,
I am running simulations in SE mode using the se.py with
fastforward and
switch_cpu options. I am getting an error when the number of cpus
are more
than one. The command I am running and the corresponding error
messege is
given here.
./build/ALPHA_SE/m5.opt configs/example/se.py -d --caches --l2cache
--fast-forward=100 --max-inst 100000 -n 2 -s
Filename filename
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/scratch/tripti/m5/src/python/m5/main.py", line 360, in main
exec filecode in scope
File "configs/example/se.py", line 161, in <module>
Simulation.run(options, root, system, FutureClass)
File "/scratch/tripti/m5/configs/common/Simulation.py", line 169,
in run
testsys.switch_cpus = switch_cpus
File "/scratch/tripti/m5/src/python/m5/SimObject.py", line 621, in
__setattr__
self.add_child(attr, value)
File "/scratch/tripti/m5/src/python/m5/SimObject.py", line 668, in
add_child
(name, child._name, child._parent)
AttributeError: 'SimObjectVector' object has no attribute '_name'
What else need to be modified?
thanks and regards,
Tripti Warrier
IIT M
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://m5sim.org/cgi-bin/mailman/private/m5-users/attachments/20110323/74daa33d/attachment-0001.html>
------------------------------
Message: 2
Date: Wed, 23 Mar 2011 07:59:47 -0400
From: Anthony Gutierrez <[email protected]
<mailto:[email protected]>>
To: m5-users <[email protected] <mailto:[email protected]>>
Subject: Re: [m5-users] SE mode with switch_cpu and multiple cpus.
Message-ID: <[email protected]
<mailto:[email protected]>>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Tripti,
I submitted a patch for this on the review board a few weeks ago.
I just
need to ship it, but you should be able to get it from there.
-Tony
------------------------------
Message: 3
Date: Wed, 23 Mar 2011 10:14:22 -0500
From: sheng qiu <[email protected]
<mailto:[email protected]>>
To: [email protected] <mailto:[email protected]>
Subject: [m5-users] question about the DRAM model in M5
Message-ID:
<[email protected]
<mailto:[email protected]>>
Content-Type: text/plain; charset="iso-8859-1"
Hi all,
i have a simple question. if we have more requests on DRAM during some
period, will the access latency become larger because of the bursts of
requests? or does M5 consider the queuing delay for the DRAM access?
Thanks,
Sheng
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://m5sim.org/cgi-bin/mailman/private/m5-users/attachments/20110323/7b5e3bb5/attachment-0001.html>
------------------------------
_______________________________________________
m5-users mailing list
[email protected] <mailto:[email protected]>
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
End of m5-users Digest, Vol 56, Issue 31
****************************************
--
Regards,
Tripti
_______________________________________________
m5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
