Hi Soumyaroop, Do you, or someone else, can say what needs to be done to make InOrderCPU work with SPARC? What needs to be adapted, filenames... hints?
Eberle On Tue, Jun 22, 2010 at 11:34 AM, soumyaroop roy <[email protected]> wrote: > Hello Eberle: > > On Tue, Jun 22, 2010 at 10:04 AM, Eberle <[email protected]> wrote: > > I've read the thread about SPARC_FS and InOrderCPU, but I need to know > > whether it works with SPARC_SE. > > Currently, SPARC ISA is not supported in InOrderCPU > (http://m5sim.org/wiki/index.php/InOrder_ToDo_List). FS is currently > not supported for any ISA. > > > > > > > And also: The TimingSimpleCPU is equivalent to InOrderCPU, in terms of > > pipeline and memory access (reordering)? > > TimingSimpleCPU does not model a CPU pipeline. > > Please refer to the documentation of these CPUs here: > > TimingSimpleCPU: > http://m5sim.org/wiki/index.php/SimpleCPU > > InOrderCpu: > http://m5sim.org/wiki/index.php/InOrder > > > > > > > > > -- > > Eberle A. Rambo. > > regards, > Soumyaroop > > > > > _______________________________________________ > > m5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > > > -- > Soumyaroop Roy > Ph.D. Candidate > Department of Computer Science and Engineering > University of South Florida, Tampa > http://www.csee.usf.edu/~sroy <http://www.csee.usf.edu/%7Esroy> > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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