Hello all,
I tried to test instruction prefetcher of CPU I-Cache in gem5 with the
following config script.
import m5
from m5.objects import *
class L1Cache(Cache):
tag_latency = 1
data_latency = 1
response_latency = 1
mshrs = 4
tgts_per_mshr = 20
def connectCPU(self, cpu):
raise NotImplementedError
def connectBus(self, bus):
self.mem_side = bus.cpu_side_ports
class L1ICache(L1Cache):
assoc = 4
size = '32kB'
is_read_only = True
def connectCPU(self, cpu):
self.cpu_side = cpu.icache_port
class L1DCache(L1Cache):
assoc = 4
size = '32kB'
def connectCPU(self, cpu):
self.cpu_side = cpu.dcache_port
class L2Cache(Cache):
assoc = 8
size = '256kB'
tag_latency = 10
data_latency = 10
response_latency = 10
mshrs = 20
tgts_per_mshr = 12
def connectCPUSideBus(self, bus):
self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
self.mem_side = bus.cpu_side_ports
system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('8GB')]
system.cpu = O3CPU()
system.cpu.icache = L1ICache()
system.cpu.dcache = L1DCache()
system.cpu.icache.connectCPU(system.cpu)
system.cpu.dcache.connectCPU(system.cpu)
system.l2bus = L2XBar()
system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)
system.cpu.dcache.prefetcher = StridePrefetcher()
system.cpu.icache.prefetch_on_access = True
system.cpu.icache.prefetch_on_pf_hit = True
system.cpu.icache.prefetcher = PIFPrefetcher()
system.l2cache = L2Cache()
system.l2cache.connectCPUSideBus(system.l2bus)
system.membus = SystemXBar()
system.l2cache.connectMemSideBus(system.membus)
system.cpu.createInterruptController()
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
system.system_port = system.membus.cpu_side_ports
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.mem_side_ports
process = Process()
binpath = 'tests/test-progs/hello/bin/x86/linux/hello'
process.cmd = [binpath]
system.workload = SEWorkload.init_compatible(binpath)
system.cpu.workload = process
system.cpu.createThreads()
root = Root(full_system = False, system = system)
m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
But the stats.txt showed that the icache.prefetcher is not triggered at all.
system.cpu.icache.prefetcher.demandMshrMisses 334
# demands not covered by prefetchs (Count)
system.cpu.icache.prefetcher.pfIssued 0 #
number of hwpf issued (Count)
system.cpu.icache.prefetcher.pfUseful 0 #
number of useful prefetch (Count)
system.cpu.icache.prefetcher.pfUsefulButMiss 0
# number of hit on prefetch but cache block is not in an usable state (Count)
system.cpu.icache.prefetcher.accuracy nan #
accuracy of the prefetcher (Count)
system.cpu.icache.prefetcher.coverage 0 #
coverage brought by this prefetcher (Count)
I also tested some other programs besides hello-world, and in all of them
instruction prefetcher is not triggered.
In BaseCache::getNextQueueEntry() in src/mem/cache/base.cc, I found that
prefetcher is triggered only when mshrQueue and writeBuffer are both empty.
assert(!miss_mshr && !wq_entry);
if (prefetcher && mshrQueue.canPrefetch() && !isBlocked()) {
// If we have a miss queue slot, we can try a prefetch
PacketPtr pkt = prefetcher->getPacket();
.....
With some DPRINTF, I found that for icache, almost every time the
getNextQueueEntry() was called, there was 1 entry in its mshrQueue. So, it
seems that instruction prefetcher will never be triggered with such priority.
Does anyone ever make icache.prefetcher work with some configuration? Or do I
have to modify the source code to achieve that?
I would appreciate any ideas. Thanks in advance!
Guangda
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